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| 500 mhz, triple 16 9 video crosspoint switch data sheet ad8175 rev. b information furnished by analog devices is believed to be accurate and reliable. however, no responsibility is assumed by analog devices for its use, nor for any infringements of patents or other rights of third parties that may result from its use. specif ications subject to change without notice. no license is granted by implication or otherwise under any patent or patent rights of analog devices. trademarks and registered trademarks are the property of their respective owners. one technology way, p.o. box 9106, norwood, ma 02062 - 9106, u.s.a. tel: 781.329.4700 www.analog.com fax: 781.461.3113 ? 2007 C 2011 analog devices, inc. all rights reserved. features high channel count , triple 16 9 high speed, non - blocking switch a rray differential or s ingle - ended o peration supports s ync - on c ommon - m ode and s ync - on c olor operating modes decoded hv sync outputs available g = +2 o peration ( d iff erential i nput to d ifferential o utput) flexible p ower s upplies: +5 v or 2.5 v logic ground for convenient control interface serial or p arallel p rogramming of s witch a rray high impedance output disabl e allows connection of multiple devices with minimal loading on output bus adjustable o utput cm and black level through e xternal p ins excellent ac p erformance (to support 1600 1200 @ 85 hz) bandwidth: 500 mhz slew rate: 1800 v/s settling t ime : 4 ns to 1% low power of 3.5 w low all - hostile crosstalk ? 88 db @ 5 mhz ? 46 db @ 500 mhz wide input c ommon - mode r ange of 4 v reset pin allows disabling of all outputs fully popul ated 26 x 26 ball pbga package (27 mm x 27 mm, 1 mm ball pitch) convenient grouping of rgb signals for easy routing applications rgb v ideo s witching kvm professional v ideo functional block dia gram 2 2 2 2 2 2 2 2 2 2 2 2 input receiver g = +1 output buffer g = +1 9 144 set individual, or reset all outputs to off enable/disable 45 vblk vocm_cmencon vocm_cmencoff r g b r g b 16 x rgb channels cmenc serin rst update cs clk we ser/par d0 d1 d2 d3 d4 vpos vneg vdd dgnd serout 9 x rgb, hv channels h b g r v h b g r v 45 a0 a1 a2 a3 ad8175 06478-001 1 0 switch matrix g = +2 45-bit shift register with 5-bit parallel loading decode 9 5:16 decoders parallel latch figure 1. general description the ad8175 is a high speed, triple 16 9 video crosspoint switch matrix. it supports 1600 1200 rgb displays @ 85 hz refresh rate, by offering a 500 mhz bandwidth a nd a slew rate of 1800 v/s . with ? 88 db of crosstalk and ? 94 db isolation (@ 5 mhz), th e ad8175 is useful in many high speed video applications. the ad 8 175 supports two modes of operation : differential - in to differential - out mode with sync - on cm signaling passed through the switch and differential - in to differential - out mode with cm signaling removed through the switch. the output cm and black level can be conveniently set via external pins. the independent output buffers of the ad8175 can be placed into a high impedance state to c reate larger arrays by paralleling crosspoint outputs. inputs can be paralleled as well. the ad8175 offers both serial and parallel programming modes. the ad8175 is packaged in a fully - populated 26 26 ball pbga package and is available over the extended industrial temperature range of ? 40c to +85 c .
ad8175 data sheet rev. b | page 2 of 40 table of contents features .............................................................................................. 1 applications ....................................................................................... 1 functional block diagram .............................................................. 1 gene ral description ......................................................................... 1 revision history ............................................................................... 2 specifications ..................................................................................... 3 timing characteristics (serial mode) ....................................... 5 timing characteristics (parallel mode) .................................... 6 absolute maximum ratings ............................................................ 7 thermal resistance ...................................................................... 7 power dissipation ......................................................................... 7 esd caution .................................................................................. 7 pin configuration and function descriptions ..............................8 truth table and logic diagram ............................................... 17 equivalent circuits ......................................................................... 19 typical performance characteristics ........................................... 21 theory of operation ...................................................................... 26 applications ..................................................................................... 27 operating modes ........................................................................ 27 programming .............................................................................. 28 differential and single - ended operation ............................... 30 outline dimensions ....................................................................... 39 ordering guide .......................................................................... 39 revision h istory 10/11 rev . a to rev. b changes to table 15 ........................................................................ 17 changes to parallel programming description section ............ 29 2/09 rev . 0 to rev. a updated outline dimensions ....................................................... 39 5 /07 revision 0: initial versi on data sheet ad8175 rev. b | page 3 of 40 specifications v s = 2.5 v at t a = 25c, g = +2, r l = 100 ? (each output) , vblk = 0 v, o utput cm voltage = 0 v, d ifferential i/o mode, unless otherwise no ted. table 1 . parameter conditions min typ max unit dynamic performance ? 3 db bandwidth 200 mv p -p 500 mhz 2 v p -p 450 mhz gain flatness 0.1 db, 200 mv p -p 25 mhz propagation delay 2 v p -p 1.3 ns settling time 1% , 2 v step 4 ns slew rate, differential output 2 v step 1800 v/s 2 v step, 10% to 90% 1500 v/s slew rate, rgb common mode 1 v ste p , 10% to 90% 300 v/s slew rate, hv outputs rail -to - rail, ttl load 400 v/s noise/distortion performance crosstalk, all hostile ? = 5 mhz ? 88 db ? = 10 mhz ? 82 db ? = 100 mhz ? 58 db ? = 500 mhz ? 46 db off isolation, input - output ? = 5 mhz, r l = 100 ? , one channel ? 94 db input voltage noise 0.01 mhz to 10 0 mhz 40 nv/ hz dc performance gain error 1 % gain matching r, g, b same channel 0.5 % gain temperature coefficient 40 ppm/c output characteristics output offset voltage cmenc on or off 10 mv temperature coefficient 31 v/c output offset voltage, rgb common mode cmenc on or off 10 mv temperature coefficient ? 7.6 v/c output impedance enabled, differential 1.5 ? disabled, differential 2.7 k ? output disable capacitance disabled 2 pf output leakage current disabled 1 a output voltage range no load, differential 4 v p -p output current short circuit 45 ma input characteristics input voltage range, differential mode 1 1.2 v p -p input voltage range, common mode v in = 1 v p -p , diff erential 2.25 v cmr, rgb input v out, dm / v in, cm , v in, cm = 0.5 v, cmenc off C 62 db v out, dm / v in, cm , v in, cm = 0.5 v, cmenc on ?45 db cm gain, rgb input v out, cm / v in, cm , v in, cm = 0.5 v cmenc off ?70 db v out, cm / v in, cm , v in, cm = 0.5 v, cmenc on 0 db input capacitance any switch configuration 2 pf input resistance differential 3.33 k? input offset current 1 a ad8175 data sheet rev. b | page 4 of 40 parameter conditions min typ max unit switching characteristics enable on time 50% update to 50% output 80 ns switching time, 2 v step 50% update to 50% output 70 ns power supplies supply current v pos , outputs enabled, no load 600 ma outputs disabled 290 ma vneg , outputs enabled, no load 600 ma outputs disabled 290 ma d vdd , outputs enabled, no load 4 ma supply voltage range vpos ? vneg 4.5 to 5.5 v vdd to dgnd 3.3 to 5.5 v psr v out, dm /v pos , v pos = 0.5 v ?55 db v out, dm /v neg , v neg = 0.5 v ?55 db operating temperature range temperature range operating (still air) ?40 to +85 c ja operating (still air) 15 c/w data sheet ad8175 rev. b | page 5 of 40 timing characteristi cs (serial mode) specifications subject to change without notice. table 2 . limit parameter symbol min typ max unit serial data setup time t 1 40 ns clk pulse width t 2 60 ns serial data hold time t 3 50 ns clk pulse separation t 4 140 ns clk to update delay t 5 10 ns update pulse width t 6 90 ns clk to serout valid t 7 120 ns propagation delay, update to switch on 80 ns data load time, clk = 5 mhz, serial mode 9 s rst time 140 200 ns load d at a in t o seria l register on f alling edge t 2 t 4 1 0 clk 1 0 serin out8 (d4) t 1 t 3 out8 (d3) out00 (d0) 1 = l a tched 0 = transparent update transfer d at a from seria l register t o p aralle l la tches during low leve l t 5 t 7 serout t 6 06478-002 figure 2 . timing diagram, serial mode table 3 . logic levels , v dd = 3.3 v v ih v il v oh v ol i ih i il i oh i ol ser /par, clk , serin, update ser /par, clk , serin, update serout serout ser /par, clk , serin, update ser /par, clk , serin, update serout serout 2.0 v min 0.6 v max 2.8 v min 0.4 v max 20 a max C 20 a max C 1 m a min 1 ma min table 4 . h and v logic levels, v dd = 3.3 v v oh v ol i oh i ol 2.7 v min 0.5 v max C 3 ma max 3 ma max table 5 . rst logic levels, v dd = 3.3 v v ih v il i ih i il 2.0 v min 0.6 v max ? 60 a max ? 120 a max table 6 . cs logic levels, v dd = 3.3 v v oh v ol i ih i ol 2.0 v min 0.6 v max 100 a max 4 0 a max ad8175 data sheet rev. b | page 6 of 40 timing characteristi cs (parallel mode) specifications subject to change without notice. table 7 . limit parameter symbol min typ max unit parallel data setup time t 1 80 ns we pulse width t 2 110 ns parallel hold time t 3 150 ns we pulse separation t 4 90 ns we to update delay t 5 10 ns update pulse width t 6 90 ns propagation delay, update to switch on 80 ns rst time 140 200 ns t 2 t 4 1 0 we 1 0 t 1 t 3 1 = l a tched 0 = transparent update t 6 d0 t o d4 a0 t o a4 t 5 06478-003 figure 3 . timing diagram, parallel mode table 8 . logic levels, v dd = 3.3 v v ih v il v oh v ol i ih i il i oh i ol ser /par, we , d0, d1, d2, d3, d4, a0, a1, a2, a3, update ser /par, we , d0, d1, d2, d3, d4, a0, a1, a2, a3, update serout serout ser /par, we , d0, d1, d2, d3, d4, a0, a1, a2, a3, update ser /par, we , d0, d1, d2, d3, d4, a0, a1, a2, a3, update serout serout 2.0 v min 0.6 v max disabled disabled 20 a max ?20 a max disabled disabled table 9 . h and v logic levels, v dd = 3.3 v v oh v ol i oh i ol 2.7 v min 0.5 v max C 3 ma max 3 ma max table 10. rst logic levels, v dd = 3.3 v v ih v il i ih i il 2.0 v min 0.6 v max ?60 a max ?120 a max table 11. cs logic levels, v dd = 3.3 v v oh v ol i ih i ol 2.0 v min 0.6 v max 100 a max 40 a max data sheet ad8175 rev. b | page 7 of 40 absolute maximum rat ings table 12. parameter rating analog supply voltage (v pos C v neg ) +6 v digital supply voltage (v dd C d gnd ) +6 v ground p otential d ifference (v neg C d gnd ) +0.5 v to ? 2.5 v maximum p otential d ifference (v dd C v neg ) +8 v common - mode analog input voltage (v neg C 0.5 v) to (v pos + 0.5 v) differential analog input voltage 2 v digital input voltage v dd output voltage (disabled analog output) (v pos C 1 v) to (v neg + 1 v) output short - circuit duration momentary storage temperature ?65c to +125c operating temperature range ?40c to +85c lead temperature (soldering 10 sec) 300c junction temperature 150c stresses above those listed under absolute maximum ratings may cause permanent damage to the device. this is a stress rating only; functional operation of the device at these or any other conditions above those indicated in the operational section of this specification is not implied. exposure to absolute maximum rating conditions for extended periods may affect device reliability. thermal resistance ja is specified for the worst - case conditions, tha t is, a device soldered in a circuit board for surface - mount packages. table 13 . thermal resistance package type ja unit pbga 15 c/w power dissipation the ad8175 is operated with 2.5 v or +5 v supplies and can drive loads down to 100 , resulting in a large range of possible power dissipations. for this reason, extra care must be taken derating the op erating conditions based on ambient temperature . packaged in a 676 - lead bga, the ad8175 junction - to - ambient thermal impedance ( j a ) is 15c/w. for long - term reliability, the maximum allowed junction temperature of the die should not exceed 150c. temporarily exceeding this limit may cause a shift in parametric performance due to a change in stresses exerted on the die by the package . exceeding a junction temperature of 175c for an extended period can result in device failure. the following curve shows the range of allowed internal die power dissipations that meet these conditions over the ?40c to +85c ambient temperature range. wh en using table 12 , do not include external load power in the maximum power calculation, but do include load current dropped on the die output transistors. 06478-004 ambient temperature (c) maximum power (w) 3 4 5 6 7 8 9 10 15 25 35 45 55 65 75 85 t j = 150c figure 4 . maximum die power dissipation vs. ambient temperature esd caution ad8175 data sheet rev. b | page 8 of 40 pin configuration and function descrip tions 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 a vneg vneg vneg opr7 onb7 vneg opr8 onb8 vpos ipr8 inb8 vneg ipr9 inb9 vpos ipr10 inb10 vneg ipr11 inb11 vpos ipr12 inb12 vneg vneg vneg a b vneg vneg vneg onr7 opb7 vneg onr8 opb8 vpos inr8 ipb8 vneg inr9 ipb9 vpos inr10 ipb10 vneg inr11 ipb11 vpos inr12 ipb12 vneg vneg vneg b c vneg vneg vneg opg7 ong7 vneg opg8 ong8 vpos ipg8 ing8 vneg ipg9 ing9 vpos ipg10 ing10 vneg ipg11 ing11 vpos ipg12 ing12 vneg vneg vneg c d vneg vneg vneg h7 v7 vpos h8 v8 vpos vpos vpos vpos vpos vpos vpos vpos vpos vpos vpos vpos vpos vpos vpos ipg13 inr13 ipr13 d e vneg vneg vneg vpos vpos vpos vpos vpos dgnd vdd serout cs clk serin ser/par a3 a2 a1 a0 vdd dgnd vpos vpos ing13 ipb13 inb13 e f vpos vpos vpos vpos vpos vpos vpos vpos vpos vpos vpos vpos vpos vpos vpos vpos vpos vpos vpos vpos vpos vpos vpos vpos vpos vpos f g onb6 opb6 ong6 v6 vpos vpos vpos vpos vpos vpos vpos vpos vpos vpos vpos vpos vpos vpos vpos vpos vpos vpos vpos vpos vpos vpos g h opr6 onr6 opg6 h6 vpos vpos vneg vneg vneg vneg vneg vneg vneg vneg vneg vneg vneg vneg vneg vpos vpos vpos vpos ipg14 inr14 ipr14 h j vneg vneg vneg vpos vpos vpos vneg vneg vneg vneg vneg vneg vneg vneg vneg vneg vneg vneg vneg vpos vpos vpos vpos ing14 ipb14 inb14 j k onb5 opb5 ong5 v5 vpos vpos vneg vneg vneg vneg vneg vneg vneg vneg vneg vneg vneg vneg vneg vpos vpos vpos vpos vneg vneg vneg k l opr5 onr5 opg5 h5 vpos vpos vneg vneg vneg vneg vneg vneg vneg vneg vneg vneg vneg vneg vneg vpos vpos vpos vpos ipg15 inr15 ipr15 l m vpos vpos vpos vpos vpos vpos vneg vneg vneg vneg vneg vneg vneg vneg vneg vneg vneg vneg vneg vpos vpos vpos vpos ing15 ipb15 inb15 m n onb4 opb4 ong4 v4 vpos vpos vneg vneg vneg vneg vneg vneg vneg vneg vneg vneg vneg vneg vneg vpos vpos vpos vpos vpos vpos n p opr4 onr4 opg4 h4 vpos vpos vneg vneg vneg vneg vneg vneg vneg vneg vneg vneg vneg vneg vneg vpos vpos vblk vpos vpos vpos vpos p r vneg vneg vneg vpos vpos vpos vneg vneg vneg vneg vneg vneg vneg vneg vneg vneg vneg vneg vneg vpos vpos vpos ipg7 inr7 ipr7 r t onb3 opb3 ong3 v3 vpos vpos vneg vneg vneg vneg vneg vneg vneg vneg vneg vneg vneg vneg vneg vpos vpos vpos vpos ing7 ipb7 inb7 t u opr3 onr3 opg3 h3 vpos vpos vneg vneg vneg vneg vneg vneg vneg vneg vneg vneg vneg vneg vneg vpos vpos vpos vpos vneg vneg vneg u v vpos vpos vpos vpos vpos vpos vneg vneg vneg vneg vneg vneg vneg vneg vneg vneg vneg vneg vneg vpos vpos vpos vpos ipg6 inr6 ipr6 v w onb2 opb2 ong2 v2 vpos vpos vneg vneg vneg vneg vneg vneg vneg vneg vneg vneg vneg vneg vneg vpos vpos vpos vpos ing6 ipb6 inb6 w y opr2 onr2 opg2 h2 vpos vpos vpos vpos vpos vpos vpos vpos vpos vpos vpos vpos vpos vpos vpos vpos vpos vpos vpos vpos vpos vpos y aa vneg vneg vneg vpos vpos vpos vpos vpos vpos vpos vpos vpos vpos vpos vpos vpos vpos vpos vpos vpos vpos vpos vpos vpos vpos vpos aa ab vneg vneg vneg vpos vpos vpos vpos vpos dgnd vdd rst update we cmenc d4 d3 d2 d1 d0 vdd dgnd vpos vpos ipg5 inr5 ipr5 ab ac vneg vneg vneg v1 h1 vpos v0 h0 vpos vpos vpos vpos vpos vpos vpos vpos vpos vpos vpos vpos vpos vpos vpos ing5 ipb5 inb5 ac ad vneg vneg vneg ong1 opg1 vpos ong0 opg0 vneg ing0 ipg0 vpos ing1 ipg1 vneg ing2 ipg2 vpos ing3 ipg3 vneg ing4 ipg4 vneg vneg vneg ad ae vneg vneg vneg opb1 onr1 vpos opb0 onr0 vneg ipb0 inr0 vpos ipb1 inr1 vneg ipb2 inr2 vpos ipb3 inr3 vneg ipb4 inr4 vneg vneg vneg ae af vneg vneg vneg onb1 opr1 vpos onb0 opr0 vneg inb0 ipr0 vpos inb1 ipr1 vneg inb2 ipr2 vpos inb3 ipr3 vneg inb4 ipr4 vneg vneg vneg af 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 06478-005 vocm_ cmencon vocm _ cmencoff figure 5. package bottom view data sheet ad8175 rev. b | page 9 of 40 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 a vneg vneg vneg inb12 ipr12 vpos inb11 ipr11 vneg inb10 ipr10 vpos inb9 ipr9 vneg inb8 ipr8 vpos onb8 opr8 vneg onb7 opr7 vneg vneg vneg a b vneg vneg vneg ipb12 inr12 vpos ipb11 inr11 vneg ipb10 inr10 vpos ipb9 inr9 vneg ipb8 inr8 vpos opb8 onr8 vneg opb7 onr7 vneg vneg vneg b c vneg vneg vneg ing12 ipg12 vpos ing11 ipg11 vneg ing10 ipg10 vpos ing9 ipg9 vneg ing8 ipg8 vpos ong8 opg8 vneg ong7 opg7 vneg vneg vneg c d ipr13 inr13 ipg13 vpos vpos vpos vpos vpos vpos vpos vpos vpos vpos vpos vpos vpos vpos vpos v8 h8 vpos v7 h7 vneg vneg vneg d e inb13 ipb13 ing13 vpos vpos dgnd vdd a0 a1 a2 a3 ser/par serin clk serout vdd dgnd vpos vpos vpos vpos vpos vneg vneg vneg e f vpos vpos vpos vpos vpos vpos vpos vpos vpos vpos vpos vpos vpos vpos vpos vpos vpos vpos vpos vpos vpos vpos vpos vpos vpos vpos f g vpos vpos vpos vpos vpos vpos vpos vpos vpos vpos vpos vpos vpos vpos vpos vpos vpos vpos vpos vpos vpos vpos v6 ong6 opb6 onb6 g h ipr14 inr14 ipg14 vpos vpos vpos vpos vneg vneg vneg vneg vneg vneg vneg vneg vneg vneg vneg vneg vneg vpos vpos h6 opg6 onr6 opr6 h j inb14 ipb14 ing14 vpos vpos vpos vpos vneg vneg vneg vneg vneg vneg vneg vneg vneg vneg vneg vneg vneg vpos vpos vpos vneg vneg vneg j k vneg vneg vneg vpos vpos vpos vpos vneg vneg vneg vneg vneg vneg vneg vneg vneg vneg vneg vneg vneg vpos vpos v5 ong5 opb5 onb5 k l ipr15 inr15 ipg15 vpos vpos vpos vpos vneg vneg vneg vneg vneg vneg vneg vneg vneg vneg vneg vneg vneg vpos vpos h5 opg5 onr5 opr5 l m inb15 ipb15 ing15 vpos vpos vpos vpos vneg vneg vneg vneg vneg vneg vneg vneg vneg vneg vneg vneg vneg vpos vpos vpos vpos vpos vpos m n vpos vpos vpos vpos vocm_ cmencon vpos vpos vneg vneg vneg vneg vneg vneg vneg vneg vneg vneg vneg vneg vneg vpos vpos v4 ong4 opb4 onb4 n p vpos vpos vpos vpos vblk vpos vpos vneg vneg vneg vneg vneg vneg vneg vneg vneg vneg vneg vneg vneg vpos vpos h4 opg4 onr4 opr4 p r ipr7 inr7 ipg7 vpos vocm _ cmencoff vpos vpos vneg vneg vneg vneg vneg vneg vneg vneg vneg vneg vneg vneg vneg vpos vpos vpos vneg vneg vneg r t inb7 ipb7 ing7 vpos vpos vpos vpos vneg vneg vneg vneg vneg vneg vneg vneg vneg vneg vneg vneg vneg vpos vpos v3 ong3 opb3 onb3 t u vneg vneg vneg vpos vpos vpos vpos vneg vneg vneg vneg vneg vneg vneg vneg vneg vneg vneg vneg vneg vpos vpos h3 opg3 onr3 opr3 u v ipr6 inr6 ipg6 vpos vpos vpos vpos vneg vneg vneg vneg vneg vneg vneg vneg vneg vneg vneg vneg vneg vpos vpos vpos vpos vpos vpos v w inb6 ipb6 ing6 vpos vpos vpos vpos vneg vneg vneg vneg vneg vneg vneg vneg vneg vneg vneg vneg vneg vpos vpos v2 ong2 opb2 onb2 w y vpos vpos vpos vpos vpos vpos vpos vpos vpos vpos vpos vpos vpos vpos vpos vpos vpos vpos vpos vpos vpos vpos h2 opg2 onr2 opr2 y aa vpos vpos vpos vpos vpos vpos vpos vpos vpos vpos vpos vpos vpos vpos vpos vpos vpos vpos vpos vpos vpos vpos vpos vneg vneg vneg aa ab ipr5 inr5 ipg5 vpos vpos dgnd vdd d0 d1 d2 d3 d4 cmenc vdd dgnd vpos vpos vpos vpos vpos vneg vneg vneg ab ac inb5 ipb5 ing5 vpos vpos vpos vpos vpos vpos vpos vpos vpos vpos vpos vpos vpos vpos vpos h0 v0 vpos h1 v1 vneg vneg vneg ac ad vneg vneg vneg ipg4 ing4 vneg ipg3 ing3 vpos ipg2 ing2 vneg ipg1 ing1 vpos ipg0 ing0 vneg opg0 ong0 vpos opg1 ong1 vneg vneg vneg ad ae vneg vneg vneg inr4 ipb4 vneg inr3 ipb3 vpos inr2 ipb2 vneg inr1 ipb1 vpos inr0 ipb0 vneg onr0 opb0 vpos onr1 opb1 vneg vneg vneg ae af vneg vneg vneg ipr4 inb4 vneg ipr3 inb3 vpos ipr2 inb2 vneg ipr1 inb1 vpos ipr0 inb0 vneg opr0 onb0 vpos opr1 onb1 vneg vneg vneg af 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 06478-006 cs update rst we figure 6. package top view ad8175 data sheet rev. b | page 10 of 40 table 14 . ball grid description ball no. mnemonic description a1 vneg negative analog power supply. a2 vneg negative analog power supply. a3 vneg negative analog power supply. a4 inb12 input number 12, negative phase. a5 ipr12 input number 12, positive phase. a6 vpos positive analog power supply. a7 inb11 input number 11, negative phase. a8 ipr11 input number 11, positive phase. a9 vneg negative analog power supply. a10 inb10 input number 10, negative phase. a11 ipr10 input number 10, positive phase. a12 vpos positive analog power supply. a13 inb9 input number 9, negative phase. a14 ipr9 input number 9, positive phase. a15 vneg negative analog power supply. a16 inb8 input number 8, negative phase. a17 ipr8 input number 8, positive phase. a18 vpos positive analog power supply. a19 onb8 output number 8, negative phase. a20 opr8 output number 8, positive phase. a21 vneg negative analog power supply. a22 onb7 output number 7, negative phase. a23 opr7 output number 7, positive phase. a24 vneg negative analog power supply. a25 vneg negative analog power supply. a26 vneg negative analog power supply. b1 vneg negative analog power supply. b2 vneg negative analog power supply. b3 vneg negative analog power supply. b4 ipb12 input number 12, positive phase. b5 inr12 input number 12, negative phase. b6 vpos positive analog power supply. b7 ipb11 input number 11, positive phase. b8 inr11 input number 11, negative phase. b9 vneg negative analog power supply. b10 ipb10 input number 10, positive phase. b11 inr10 input number 10, negative phase. b12 vpos positive analog power supply. b13 ipb9 input number 9, positive phase. b14 inr9 input number 9, negative phase. b15 vneg negative analog power supply. b16 ipb8 input number 8, positive phase. b17 inr8 input number 8, negative phase. b18 vpos positive analog power supply. b19 opb8 output number 8, positive phase. b20 onr8 output number 8, negative phase. b21 vneg negative analog power supply. b22 opb7 output number 7, positive phase. b23 onr7 output number 7, negative phase. b24 vneg negative analog power supply. b25 vneg negative analog power supply. ball no. mnemonic description b26 vneg negative analog power supply. c1 vneg negative analog power supply. c2 vneg negative analog power supply. c3 vneg negative analog power supply. c4 ing12 input number 12, negative phase. c5 ipg12 input number 12, positive phase. c6 vpos positive analog power supply. c7 ing11 input number 11, negative phase. c8 ipg11 input number 11, positive phase. c9 vneg negative analog power supply. c10 ing10 input number 10, negative phase. c11 ipg10 input number 10, positive phase. c12 vpos positive analog power supply. c13 ing9 input number 9, negative phase. c14 ipg9 input number 9, positive phase. c15 vneg negative analog power supply. c16 ing8 input number 8, negative phase. c17 ipg8 input number 8, positive phase. c18 vpos positive analog power supply. c19 ong8 output number 8, negative phase. c20 opg8 output number 8, positive phase. c21 vneg negative analog power supply. c22 ong7 output number 7, negative phase. c23 opg7 output number 7, positive phase. c24 vneg negative analog power supply. c25 vneg negative analog power supply. c26 vneg negative analog power supply. d1 ipr13 input number 13, positive phase. d2 inr13 input number 13, negative phase. d3 ipg13 input number 13, positive phase. d4 vpos positive analog power supply. d5 vpos positive analog power supply. d6 vpos positive analog power supply. d7 vpos positive analog power supply. d8 vpos positive analog power supply. d9 vpos positive analog power supply. d10 vpos positive analog power supply. d11 vpos positive analog power supply. d12 vpos positive analog power supply. d13 vpos positive analog power supply. d14 vpos positive analog power supply. d15 vpos positive analog power supply. d16 vpos positive analog power supply. d17 vpos positive analog power supply. d18 vpos positive analog power supply. d19 v8 output number 8, v sync. d20 h8 output number 8, h sync. d21 vpos positive analog power supply. d22 v7 output number 7, v sync. d23 h7 output number 7, h sync. d24 vneg negative analog power supply. data sheet ad8175 rev. b | page 11 of 40 ball no. mnemonic description d25 vneg negative analog power supply. d26 vneg negative analog power supply. e1 inb13 input number 13, negative phase. e2 ipb13 input number 13, positive phase. e3 ing13 input number 13, negative phase. e4 vpos positive analog power supply. e5 vpos positive analog power supply. e6 dgnd digital power supply . e7 vdd digital power supply . e8 a0 control pin 0, output address bit 0 . e9 a1 control pin 1, output address bit 1 . e10 a2 control pin 2, output address bit 2 . e11 a3 control pin 3, output address bit 3 . e12 ser / par control pin : ser ial p arallel s elect m ode . e13 serin control pin : s erial d ata i n . e14 clk control pin : s erial d ata c lock . e15 cs control pin : c hip s elect . e16 serout control pin: s erial d ata o ut . e17 vdd digital power supply . e18 dgnd digital power supply . e19 vpos positive analog power supply. e20 vpos positive analog power supply. e21 vpos positive analog power supply. e22 vpos positive analog power supply. e23 vpos positive analog power supply. e24 vneg negative analog power supply. e25 vneg negative analog power supply. e26 vneg negative analog power supply. f1 vpos positive analog power supply. f2 vpos positive analog power supply. f3 vpos positive analog power supply. f4 vpos positive analog power supply. f5 vpos positive analog power supply. f6 vpos positive analog power supply. f7 vpos positive analog power supply. f8 vpos positive analog power supply. f9 vpos positive analog power supply. f10 vpos positive analog power supply. f11 vpos positive analog power supply. f12 vpos positive analog power supply. f13 vpos positive analog power supply. f14 vpos positive analog power supply. f15 vpos positive analog power supply. f16 vpos positive analog power supply. f17 vpos positive analog power supply. f18 vpos positive analog power supply. f19 vpos positive analog power supply. f20 vpos positive analog power supply. f21 vpos positive analog power supply. f22 vpos positive analog power supply. f23 vpos positive analog power supply. f24 vpos positive analog power supply. ball no. mnemonic description f25 vpos positive analog power supply. f26 vpos positive analog power supply. g1 vpos positive analog power supply. g2 vpos positive analog power supply. g3 vpos positive analog power supply. g4 vpos positive analog power supply. g5 vpos positive analog power supply. g6 vpos positive analog power supply. g7 vpos positive analog power supply. g8 vpos positive analog power supply. g9 vpos positive analog power supply. g10 vpos positive analog power supply. g11 vpos positive analog power supply. g12 vpos positive analog power supply. g13 vpos positive analog power supply. g14 vpos positive analog power supply. g15 vpos positive analog power supply. g16 vpos positive analog power supply. g17 vpos positive analog power supply. g18 vpos positive analog power supply. g19 vpos positive analog power supply. g20 vpos positive analog power supply. g21 vpos positive analog power supply. g22 vpos positive analog power supply. g23 v6 output number 6, v sync. g24 ong6 output number 6, negative phase. g25 opb6 output number 6, positive phase. g26 onb6 output number 6, negative phase. h1 ipr14 input number 14, positive phase. h2 inr14 input number 14, negative phase. h3 ipg14 input number 14, positive phase. h4 vpos positive analog power supply. h5 vpos positive analog power supply. h6 vpos positive analog power supply. h7 vpos positive analog power supply. h8 vneg negative analog power supply. h9 vneg negative analog power supply. h10 vneg negative analog power supply. h11 vneg negative analog power supply. h12 vneg negative analog power supply. h13 vneg negative analog power supply. h14 vneg negative analog power supply. h15 vneg negative analog power supply. h16 vneg negative analog power supply. h17 vneg negative analog power supply. h18 vneg negative analog power supply. h19 vneg negative analog power supply. h20 vneg negative analog power supply. h21 vpos positive analog power supply. h22 vpos positive analog power supply. h23 h6 output number 6, h sync. h24 opg6 output number 6, positive phase. ad8175 data sheet rev. b | page 12 of 40 ball no. mnemonic description h25 onr6 output number 6, negative phase. h26 opr6 output number 6, positive phase. j1 inb14 input number 14, negative phase. j2 ipb14 input number 14, positive phase. j3 ing14 input number 14, negative phase. j4 vpos positive analog power supply. j5 vpos positive analog power supply. j6 vpos positive analog power supply. j7 vpos positive analog power supply. j8 vneg negative analog power supply. j9 vneg negative analog power supply. j10 vneg negative analog power supply. j11 vneg negative analog power supply. j12 vneg negative analog power supply. j13 vneg negative analog power supply. j14 vneg negative analog power supply. j15 vneg negative analog power supply. j16 vneg negative analog power supply. j17 vneg negative analog power supply. j18 vneg negative analog power supply. j19 vneg negative analog power supply. j20 vneg negative analog power supply. j21 vpos positive analog power supply. j22 vpos positive analog power supply. j23 vpos positive analog power supply. j24 vneg negative analog power supply. j25 vneg negative analog power supply. j26 vneg negative analog power supply. k1 vneg negative analog power supply. k2 vneg negative analog power supply. k3 vneg negative analog power supply. k4 vpos positive analog power supply. k5 vpos positive analog power supply. k6 vpos positive analog power supply. k7 vpos positive analog power supply. k8 vneg negative analog power supply. k9 vneg negative analog power supply. k10 vneg negative analog power supply. k11 vneg negative analog power supply. k12 vneg negative analog power supply. k13 vneg negative analog power supply. k14 vneg negative analog power supply. k15 vneg negative analog power supply. k16 vneg negative analog power supply. k17 vneg negative analog power supply. k18 vneg negative analog power supply. k19 vneg negative analog power supply. k20 vneg negative analog power supply. k21 vpos positive analog power supply. k22 vpos positive analog power supply. k23 v5 output number 5, v sync. k24 ong5 output number 5, negative phase. ball no. mnemonic description k25 opb5 output number 5, positive phase. k26 onb5 output number 5, negative phase. l1 ipr15 input number 15, positive phase. l2 inr15 input number 15, negative phase. l3 ipg15 input number 15, positive phase. l4 vpos positive analog power supply. l5 vpos positive analog power supply. l6 vpos positive analog power supply. l7 vpos positive analog power supply. l8 vneg negative analog power supply. l9 vneg negative analog power supply. l10 vneg negative analog power supply. l11 vneg negative analog power supply. l12 vneg negative analog power supply. l13 vneg negative analog power supply. l14 vneg negative analog power supply. l15 vneg negative analog power supply. l16 vneg negative analog power supply. l17 vneg negative analog power supply. l18 vneg negative analog power supply. l19 vneg negative analog power supply. l20 vneg negative analog power supply. l21 vpos positive analog power supply. l22 vpos positive analog power supply. l23 h5 output number 5, h sync. l24 opg5 output number 5, positive phase. l25 onr5 output number 5, negative phase. l26 opr5 output number 5, positive phase. m1 inb15 input number 15, negative phase. m2 ipb15 input number 15, positive phase. m3 ing15 input number 15, negative phase. m4 vpos positive analog power supply. m5 vpos positive analog power supply. m6 vpos positive analog power supply. m7 vpos positive analog power supply. m8 vneg negative analog power supply. m9 vneg negative analog power supply. m10 vneg negative analog power supply. m11 vneg negative analog power supply. m12 vneg negative analog power supply. m13 vneg negative analog power supply. m14 vneg negative analog power supply. m15 vneg negative analog power supply. m16 vneg negative analog power supply. m17 vneg negative analog power supply. m18 vneg negative analog power supply. m19 vneg negative analog power supply. m20 vneg negative analog power supply. m21 vpos positive analog power supply. m22 vpos positive analog power supply. m23 vpos positive analog power supply. m24 vpos positive analog power supply. data sheet ad8175 rev. b | page 13 of 40 ball no. mnemonic description m25 vpos positive analog power supply. m26 vpos positive analog power supply. n1 vpos positive analog power supply. n2 vpos positive analog power supply. n3 vpos positive analog power supply. n4 vpos positive analog power supply. n5 vocm_ cmencon output cm r eference with cm e ncoding o n . n6 vpos positive analog power supply. n7 vpos positive analog power supply. n8 vneg negative analog power supply. n9 vneg negative analog power supply. n10 vneg negative analog power supply. n11 vneg negative analog power supply. n12 vneg negative analog power supply. n13 vneg negative analog power supply. n14 vneg negative analog power supply. n15 vneg negative analog power supply. n16 vneg negative analog power supply. n17 vneg negative analog power supply. n18 vneg negative analog power supply. n19 vneg negative analog power supply. n20 vneg negative analog power supply. n21 vpos positive analog power supply. n22 vpos positive analog power supply. n23 v4 output number 4, v sync. n24 ong4 output number 4, negative phase. n25 opb4 output number 4, positive phase. n26 onb4 output number 4, negative phase. p1 vpos positive analog power supply. p2 vpos positive analog power supply. p3 vpos positive analog power supply. p4 vpos positive analog power supply. p5 vblk output b lank l evel . p6 vpos positive analog power supply. p7 vpos positive analog power supply. p8 vneg negative analog power supply. p9 vneg negative analog power supply. p10 vneg negative analog power supply. p11 vneg negative analog power supply. p12 vneg negative analog power supply. p13 vneg negative analog power supply. p14 vneg negative analog power supply. p15 vneg negative analog power supply. p16 vneg negative analog power supply. p17 vneg negative analog power supply. p18 vneg negative analog power supply. p19 vneg negative analog power supply. p20 vneg negative analog power supply. p21 vpos positive analog power supply. p22 vpos positive analog power supply. p23 h4 output number 4, h sync. p24 opg4 output number 4, positive phase. ball no. mnemonic description p25 onr4 output number 4, negative phase. p26 opr4 output number 4, positive phase. r1 ipr7 input number 7, positive phase. r2 inr7 input number 7, negative phase. r3 ipg7 input number 7, positive phase. r4 vpos positive analog power supply. r5 vocm_ cmencoff output r eference with cm e ncoding o ff . r6 vpos positive analog power supply. r7 vpos positive analog power supply. r8 vneg negative analog power supply. r9 vneg negative analog power supply. r10 vneg negative analog power supply. r11 vneg negative analog power supply. r12 vneg negative analog power supply. r13 vneg negative analog power supply. r14 vneg negative analog power supply. r15 vneg negative analog power supply. r16 vneg negative analog power supply. r17 vneg negative analog power supply. r18 vneg negative analog power supply. r19 vneg negative analog power supply. r20 vneg negative analog power supply. r21 vpos positive analog power supply. r22 vpos positive analog power supply. r23 vpos positive analog power supply. r24 vneg negative analog power supply. r25 vneg negative analog power supply. r26 vneg negative analog power supply. t1 inb7 input number 7, negative phase. t2 ipb7 input number 7, positive phase. t3 ing7 input number 7, negative phase. t4 vpos positive analog power supply. t5 vpos positive analog power supply. t6 vpos positive analog power supply. t7 vpos positive analog power supply. t8 vneg negative analog power supply. t9 vneg negative analog power supply. t10 vneg negative analog power supply. t11 vneg negative analog power supply. t12 vneg negative analog power supply. t13 vneg negative analog power supply. t14 vneg negative analog power supply. t15 vneg negative analog power supply. t16 vneg negative analog power supply. t17 vneg negative analog power supply. t18 vneg negative analog power supply. t19 vneg negative analog power supply. t20 vneg negative analog power supply. t21 vpos positive analog power supply. t22 vpos positive analog power supply. t23 v3 output number 3, v sync. t24 ong3 output number 3, negative phase. ad8175 data sheet rev. b | page 14 of 40 ball no. mnemonic description t25 opb3 output number 3, positive phase. t26 onb3 output number 3, negative phase. u1 vneg negative analog power supply. u2 vneg negative analog power supply. u3 vneg negative analog power supply. u4 vpos positive analog power supply. u5 vpos positive analog power supply. u6 vpos positive analog power supply. u7 vpos positive analog power supply. u8 vneg negative analog power supply. u9 vneg negative analog power supply. u10 vneg negative analog power supply. u11 vneg negative analog power supply. u12 vneg negative analog power supply. u13 vneg negative analog power supply. u14 vneg negative analog power supply. u15 vneg negative analog power supply. u16 vneg negative analog power supply. u17 vneg negative analog power supply. u18 vneg negative analog power supply. u19 vneg negative analog power supply. u20 vneg negative analog power supply. u21 vpos positive analog power supply. u22 vpos positive analog power supply. u23 h3 output number 3, h sync. u24 opg3 output number 3, positive phase. u25 onr3 output number 3, negative phase. u26 opr3 output number 3, positive phase. v1 ipr6 input number 6, positive phase. v2 inr6 input number 6, negative phase. v3 ipg6 input number 6, positive phase. v4 vpos positive analog power supply. v5 vpos positive analog power supply. v6 vpos positive analog power supply. v7 vpos positive analog power supply. v8 vneg negative analog power supply. v9 vneg negative analog power supply. v10 vneg negative analog power supply. v11 vneg negative analog power supply. v12 vneg negative analog power supply. v13 vneg negative analog power supply. v14 vneg negative analog power supply. v15 vneg negative analog power supply. v16 vneg negative analog power supply. v17 vneg negative analog power supply. v18 vneg negative analog power supply. v19 vneg negative analog power supply. v20 vneg negative analog power supply. v21 vpos positive analog power supply. v22 vpos positive analog power supply. v23 vpos positive analog power supply. v24 vpos positive analog power supply. ball no. mnemonic description v25 vpos positive analog power supply. v26 vpos positive analog power supply. w1 inb6 input number 6, negative phase. w2 ipb6 input number 6, positive phase. w3 ing6 input number 6, negative phase. w4 vpos positive analog power supply. w5 vpos positive analog power supply. w6 vpos positive analog power supply. w7 vpos positive analog power supply. w8 vneg negative analog power supply. w9 vneg negative analog power supply. w10 vneg negative analog power supply. w11 vneg negative analog power supply. w12 vneg negative analog power supply. w13 vneg negative analog power supply. w14 vneg negative analog power supply. w15 vneg negative analog power supply. w16 vneg negative analog power supply. w17 vneg negative analog power supply. w18 vneg negative analog power supply. w19 vneg negative analog power supply. w20 vneg negative analog power supply. w21 vpos positive analog power supply. w22 vpos positive analog power supply. w23 v2 output number 2, v sync. w24 ong2 output number 2, negative phase. w25 opb2 output number 2, positive phase. w26 onb2 output number 2, negative phase. y1 vpos positive analog power supply. y2 vpos positive analog power supply. y3 vpos positive analog power supply. y4 vpos positive analog power supply. y5 vpos positive analog power supply. y6 vpos positive analog power supply. y7 vpos positive analog power supply. y8 vpos positive analog power supply. y9 vpos positive analog power supply. y10 vpos positive analog power supply. y11 vpos positive analog power supply. y12 vpos positive analog power supply. y13 vpos positive analog power supply. y14 vpos positive analog power supply. y15 vpos positive analog power supply. y16 vpos positive analog power supply. y17 vpos positive analog power supply. y18 vpos positive analog power supply. y19 vpos positive analog power supply. y20 vpos positive analog power supply. y21 vpos positive analog power supply. y22 vpos positive analog power supply. y23 h2 output number 2, h sync. y24 opg2 output number 2, positive phase. data sheet ad8175 rev. b | page 15 of 40 ball no. mnemonic description y25 onr2 output number 2, negative phase. y26 opr2 output number 2, positive phase. aa1 vpos positive analog power supply. aa2 vpos positive analog power supply. aa3 vpos positive analog power supply. aa4 vpos positive analog power supply. aa5 vpos positive analog power supply. aa6 vpos positive analog power supply. aa7 vpos positive analog power supply. aa8 vpos positive analog power supply. aa9 vpos positive analog power supply. aa10 vpos positive analog power supply. aa11 vpos positive analog power supply. aa12 vpos positive analog power supply. aa13 vpos positive analog power supply. aa14 vpos positive analog power supply. aa15 vpos positive analog power supply. aa16 vpos positive analog power supply. aa17 vpos positive analog power supply. aa18 vpos positive analog power supply. aa19 vpos positive analog power supply. aa20 vpos positive analog power supply. aa21 vpos positive analog power supply. aa22 vpos positive analog power supply. aa23 vpos positive analog power supply. aa24 vneg negative analog power supply. aa25 vneg negative analog power supply. aa26 vneg negative analog power supply. ab1 ipr5 input number 5, positive phase. ab2 inr5 input number 5, negative phase. ab3 ipg5 input number 5, positive phase. ab4 vpos positive analog power supply. ab5 vpos positive analog power supply. ab6 dgnd digital power supply . ab7 vdd digital power supply . ab8 d0 control pin , input address bit 0 . ab9 d1 control pin , input address bit 1 . ab10 d2 control pin , input address bit 2 . ab11 d3 control pin , input address bit 3 . ab12 d4 control pin , input address bit 4 . ab13 cmenc control pin , p ass/ s top cm e ncoding . ab14 we control pin , 1st r ank w rite s trobe . ab15 update control pin , 2nd r ank w rite s trobe . ab16 rst control pin , 2nd r ank d ata r eset . ab17 vdd digital power supply . ab18 dgnd digital power supply . ab19 vpos positive analog power supply. ab20 vpos positive analog power supply. ab21 vpos positive analog power supply. ab22 vpos positive analog power supply. ab23 vpos positive analog power supply. ab24 vneg negative analog power supply. ball no. mnemonic description ab25 vneg negative analog power supply. ab26 vneg negative analog power supply. ac1 inb5 input number 5, negative phase. ac2 ipb5 input number 5, positive phase. ac3 ing5 input number 5, negative phase. ac4 vpos positive analog power supply. ac5 vpos positive analog power supply. ac6 vpos positive analog power supply. ac7 vpos positive analog power supply. ac8 vpos positive analog power supply. ac9 vpos positive analog power supply. ac10 vpos positive analog power supply. ac11 vpos positive analog power supply. ac12 vpos positive analog power supply. ac13 vpos positive analog power supply. ac14 vpos positive analog power supply. ac15 vpos positive analog power supply. ac16 vpos positive analog power supply. ac17 vpos positive analog power supply. ac18 vpos positive analog power supply. ac19 h0 output number 1, h sync. ac20 v0 output number 0, v sync. ac21 vpos positive analog power supply. ac22 h1 output number 1, h sync. ac23 v1 output number 1, v sync. ac24 vneg negative analog power supply. ac25 vneg negative analog power supply. ac26 vneg negative analog power supply. ad1 vneg negative analog power supply. ad2 vneg negative analog power supply. ad3 vneg negative analog power supply. ad4 ipg4 input number 4, positive phase. ad5 ing4 input number 4, negative phase. ad6 vneg negative analog power supply. ad7 ipg3 input number 3, positive phase. ad8 ing3 input number 3, negative phase. ad9 vpos positive analog power supply. ad10 ipg2 input number 2, positive phase. ad11 ing2 input number 2, negative phase. ad12 vneg negative analog power supply. ad13 ipg1 input number 1, positive phase. ad14 ing1 input number 1, negative phase. ad15 vpos positive analog power supply. ad16 ipg0 input number 0, positive phase. ad17 ing0 input number 0, negative phase. ad18 vneg negative analog power supply. ad19 opg0 output number 0, positive phase. ad20 ong0 output number 0, negative phase. ad21 vpos positive analog power supply. ad22 opg1 output number 1, positive phase. ad23 ong1 output number 1, negative phase. ad24 vneg negative analog power supply. ad8175 data sheet rev. b | page 16 of 40 ball no. mnemonic description ad25 vneg negative analog power supply. ad26 vneg negative analog power supply. ae1 vneg negative analog power supply. ae2 vneg negative analog power supply. ae3 vneg negative analog power supply. ae4 inr4 input number 4, negative phase. ae5 ipb4 input number 4, positive phase. ae6 vneg negative analog power supply. ae7 inr3 input number 3, negative phase. ae8 ipb3 input number 3, positive phase. ae9 vpos positive analog power supply. ae10 inr2 input number 2, negative phase. ae11 ipb2 input number 2, positive phase. ae12 vneg negative analog power supply. ae13 inr1 input number 1, negative phase. ae14 ipb1 input number 1, positive phase. ae15 vpos positive analog power supply. ae16 inr0 input number 0, negative phase. ae17 ipb0 input number 0, positive phase. ae18 vneg negative analog power supply. ae19 onr0 output number 0, negative phase. ae20 opb0 output number 0, positive phase. ae21 vpos positive analog power supply. ae22 onr1 output number 1, negative phase. ae23 opb1 output number 1, positive phase. ae24 vneg negative analog power supply. ae25 vneg negative analog power supply. ball no. mnemonic description ae26 vneg negative analog power supply. af1 vneg negative analog power supply. af2 vneg negative analog power supply. af3 vneg negative analog power supply. af4 ipr4 input number 4, positive phase. af5 inb4 input number 4, negative phase. af6 vneg negative analog power supply. af7 ipr3 input number 3, positive phase. af8 inb3 input number 3, negative phase. af9 vpos positive analog power supply. af10 ipr2 input number 2, positive phase. af11 inb2 input number 2, negative phase. af12 vneg negative analog power supply. af13 ipr1 input number 1, positive phase. af14 inb1 input number 1, negative phase. af15 vpos positive analog power supply. af16 ipr0 input number 0, positive phase. af17 inb0 input number 0, negative phase. af18 vneg negative analog power supply. af19 opr0 output number 0, positive phase. af20 onb0 output number 0, negative phase. af21 vpos positive analog power supply. af22 opr1 output number 1, positive phase. af23 onb1 output number 1, negative phase. af24 vneg negative analog power supply. af25 vneg negative analog power supply. af26 vneg negative analog power supply. data sheet ad8175 rev. b | page 17 of 40 truth table and logi c diagram table 15 . operation truth table we update clk serin serout rst ser /par cs cmenc operation/comment x x x x x 0 x x x asynchronous reset. all ou tputs are disabled. contents of 45 - bit shift register are unchanged. 0 1 1 x x 1 0 0 x broadcast. the data on d0 through d 4 is loaded into all locations of the 45 - bit shift register. data is not applied to switch array. 1 1 serin i serin i - 45 1 0 0 x serial mode. the data on the serin line is loaded i nto the 45- bit shift register. the first bit clocked into the shift register appears a t serout 45 clock cycles later. data is not applied to switch array. 0 1 1 x x 1 1 x x parallel mo de. the data on parallel lines d0 through d 4 is loaded into the shift register locati on addressed by a0 through a3. data is not applied to switch array. chip s elect feature is not applicable. 1 0 1 x x 1 x 0 x switch array update. data in the 45 - bit shift register is transferred to the parallel latches and applied to the switch array. 1 x x x x 1 1 0 x no change in logic. ad8175 data sheet rev. b | page 18 of 40 rst cs 06478 - 029 d 1 d 0 q s d0 d1 d2 d3 d4 d 1 d 0 q s d 1 d 0 q s d 1 d 0 q s d 1 d 0 q s update a3 a2 a1 a0 d 1 d 0 q s d q clk out1 en out0 en out8 en out2 en out3 en out4 en out5 en out6 en d 1 d 0 q s d 1 d 0 q s d 1 d 0 q s d 1 d 0 q s d 1 d 0 q s decode d 1 d 0 q s out7 en switch matrix output enable 144 9 d clr q out0 b0 ena d clr q out0 b1 ena d clr q out0 b2 ena d clr q out0 b3 ena d clr q out0 en ena d clr q out1 b0 ena d clr q out7 en ena d clr q out8 b0 ena d clr q out8 b1 ena d clr q out8 b2 ena d clr q out8 b3 ena d clr q out8 en ena parallel data (output enable) ser/par we serin clk o u t p u t addr es s 4 t o 9 d e c o d e r d q clk d q clk d q clk d q clk d q d q clk d q clk d q clk d q clk d q clk d q clk cs serout clk figure 7 . logic diagram data sheet ad8175 rev. b | page 19 of 40 equivalent circuits 1k? (vpos ? vneg) 2 1k? opn, onn 06478-007 figure 8 . enabled output (see also esd protection map , figure 19 ) 0.4pf 3.1k? 20k? 20k? 3.4pf 3.4pf opn vpos vneg 06478-008 20k? 20k? vpos vneg onn figure 9 . disabled output (see also esd protection map , figure 19 ) 1.3pf 1.3pf 0.3pf ipn inn 10k? 2500? 2500? 2525? 2525? 06478-009 figure 10 . receive r, d ifferential (see also esd protection map , figure 19 ) 1.3pf 1.3pf 0.3pf ipn inn 10k? 2500? 2500? 06478-010 figure 11 . receiver simplified equivalent circuit when driving differentially 1.6pf ipn inn 2.5k? 06478-011 figure 12 . receiver simplified equivalent circuit when driving single - ended 0.1pf vpos 10k? 0.1pf 10k? vneg vblk, vocm_cmencoff 06478-012 figure 13 . vblk and vocm_cmencoff inputs (see also esd protection map , figure 19 ) 0.3pf vpos 3.33k? 0.3pf 3.33k? vneg vocm_cmencon 06478-013 figure 14 . vocm_cmencon input (see also esd protection map , figure 19 ) rst vdd dgnd 1k? 25k? 06478-014 figure 15 . rst input (see also esd protection map , figure 19 ) clk, ser/ p ar, we, upd a te, serin a[3:0], d[4:0], cmenc dgnd 1k? 06478-015 figure 16 . logic input (see also esd protection map , figure 19 ) cs dgnd 1k? 25k? 06478-048 figure 17 . cs input (see also esd protection map, figure 19 ) ad8175 data sheet rev. b | page 20 of 40 vdd dgnd serou t , h, v 06478-016 figure 18 . serout, h, v logic output s (see also esd protection map, figure 19 ) clk, rst, ser/par, we, update, serin, serout, a[3:0], d[4:0], cmenc, cs vpos vdd vneg dgnd ipn, inn, opn, onn, vblk, vocm_cmencoff vocm_cmencon 06478-017 figure 19 . esd protection map data sheet ad8175 rev. b | page 21 of 40 t y pical performance ch aracteristics v s = 2.5 v at t a = 25c, g = +2, r l = 100 ? (each output) , vblk = 0 v, o utput cm voltage = 0 v, differential i/o mode, unless otherwise no ted. 06478-031 frequency (mhz) gain (db) ?6 ?4 ?2 0 2 4 6 8 10 12 1 10 100 1000 figure 20 . small signal frequency response, 200 mv p - p 06478-032 frequency (mhz) gain (db) 1 10 100 1000 ?6 ?4 ?2 0 2 4 6 8 10 12 figure 21 . large signal frequency response, 2 v p - p 06478-055 frequency (mhz) gain (db) ?4 ?2 0 2 4 6 8 10 12 14 16 1 10 100 1000 2pf 0pf 5pf 10pf figure 22 . small signal frequency response with capacitive loads 06478-033 time (ns) v out , diff (v) ?0.15 ?0.10 ?0.05 0 0.05 0.10 0.15 2 4 6 8 10 12 14 16 18 20 figure 23 . small signa l pulse response, 200 mv p - p 06478-034 time (ns) v out , diff (v) 2 4 6 8 10 12 14 16 18 20 ?1.5 ?1.0 ?0.5 0 0.5 1.0 1.5 figure 24 . large signal pulse response, 2 v p - p 06478-035 time (ns) output error (%) ?25 ?20 ?15 ?10 ?5 0 5 0 1 2 3 4 5 6 7 8 9 10 ?1.2 ?0.8 ?0.4 0 0.4 0.8 1.2 v out , diff (v) v in v out error figure 25 . settling time ad8175 data sheet rev. b | page 22 of 40 0 6478-047 time (ns) output error (%) ?5 ?4 ?3 ?2 ?1 0 1 2 3 4 5 012345678910 figure 26. settling time, 1% zoom 0 6478-046 time (ns) v out , diff (v) ?5 ?4 ?3 ?2 ?1 0 1 2 012345678910 ?1000 0 1000 2000 3000 4000 5000 6000 slew rate (v/s) 1850v/s peak figure 27. large signal rising edge slew rate 06478-056 frequency (mhz) crosstalk (db) 1 10 100 1000 ?120 ?100 ?80 ?60 ?40 ?20 0 figure 28. crosstalk, all hostile, single-ended 06478-057 frequency (mhz) crosstalk (db) 1 10 100 1000 ?120 ?100 ?80 ?60 ?40 ?20 0 figure 29. crosstalk, all hostile 06478-037 frequency (mhz) feedthrough (db) ?120 ?100 ?80 ?60 ?40 ?20 0 1 10 100 1000 figure 30. crosstalk, off isolation 06478-038 frequency (mhz) cmr (db) 1 10 100 1000 ?80 ?70 ?60 ?50 ?40 ?30 ?20 ?10 0 cmenc low cmenc high figure 31. common-mode rejection data sheet ad8175 rev. b | page 23 of 40 06478-043 temperature (c) |ipos| and |ineg| (ma) 0 100 200 300 400 500 600 ?50 ?40 ?30 ?20 ?10 0 10 20 30 40 50 60 70 80 90 100 |ipos| and |ineg| (all outputs disabled) |ipos| and |ineg| (broadcast) figure 32 . quiescent supply currents vs . temperature 06478-049 frequency (mhz) impedance ( ?) 1 10 100 1000 0 500 1000 1500 2000 2500 3000 figure 33 . output impedance, disabled 06478-050 frequency (mhz) impedance (?) 1 10 100 1000 0 20 40 60 80 100 120 figure 34 . output impedance , enabled 06478-051 frequency (mhz) impedance ( ?) 100 1000 10000 1 10 100 1000 figure 35 . input impedance 06478-052 frequency (mhz) impedance ( ?) 100 1000 10000 1 10 100 1000 figure 36 . input impedance, single - e nded 06478-039 frequency (mhz) balance error (db) 1 10 100 1000 ?80 ?70 ?60 ?50 ?40 ?30 ?20 ?10 0 figure 37 . output balance error ad8175 data sheet rev. b | page 24 of 40 06478-058 time (ns) v out , common mode (v) ?1.5 ?1.0 ?0.5 0 0.5 1.0 0 100 200 300 400 500 600 700 800 900 1000 ?5 0 5 10 15 20 v out (v) red vsync hsync green blue figure 38. common-mode pulse response 06478-040 frequency (mhz) feedthrough (db) 1 10 100 1000 ?90 ?80 ?70 ?60 ?50 ?40 ?30 ?20 ?10 0 figure 39. common-mode isolation, cmenc low 06478-059 frequency (mhz) noise spectral density (nv/ hz) 0 40 80 120 160 200 0 102030405060708090100 figure 40. noise spectral density 06478-041 v os (mv) count 0 250 500 750 1000 1250 1500 1750 2000 2250 2500 ?70 ?60 ?50 ?40 ?30 ?20 ?10 0 10 20 30 40 50 60 70 figure 41. v os distribution 06478-045 temperature (c) v os (mv) ?40 ?20 0 20 40 60 80 100 31v/c ?2.0 ?1.5 ?1.0 ?0.5 0 0.5 1.0 1.5 2.0 figure 42. v os drift, rto 06478-044 temperature (c) v os , common-mode (mv) ?0.6 ?0.4 ?0.2 0 0.2 0.4 0.6 ?40 ?20 0 20 40 60 80 100 ?7.6v/c figure 43. v os drift, common mode, rto data sheet ad8175 rev. b | page 25 of 40 06478-042 time (ns) update (v) ?1 0 1 2 3 4 5 6 0 20 40 60 80 100 120 140 160 180 200 220 240 260 280 ?0.2 0 0.2 0.4 0.6 0.8 1.0 1.2 v out , single-ended (v) update v out figure 44 . enable time ?0.025 ?0.020 ?0.015 ?0.010 ?0.005 0 0.005 0.010 0.015 0.020 0.025 ?40 ?20 0 20 40 60 80 100 06478-054 temperature ( c) normalized dc gain (db) 40ppm / c figure 45 . normalized dc gain vs . temperature ad8175 data sheet rev. b | page 26 of 40 theory of operation the ad8175 is a non - blocking crosspoint with 16 differential rgb input channels and nine differential rgb output channels. although the ad8175 is primarily meant for differential - in , differential - out middle - of - cat5 - run applications, each differential rgb output channel is complemented by h and v syncs for use i n end - of - cat5 - run, single - ended output applications. processing of common - mode (cm) voltage levels is achieved by placi ng the ad8175 in either of its two operation modes. in the first operation mode (cmenc low), the input cm of each rgb differential pair (possibly present either in the form of sync - on cm signaling or noise) is removed through the switch, and the output cm is set to a global reference voltage via the vocm_ cmencoff analog input. therefore, the ad8175 can behave as a differential - in , differential - out switch. if sync - on cm signaling is present at the differential rgb inputs, then the h and v outputs represent decode d syncs. in the second operation mode, input sync - on cm signaling is propagated through the switch. note that in this mode , as in the previous one, the overall input cm is blocked through the switch. in this mode , the overall output cm is set to a global r eference voltage via the vocm_cmencon analog input. in either operation mode , input pin vblk defines the black level of the positive output phase. the combination of vblk and vocm_cmencoff allows the user to position the positive and negative output phases anywhere in the allowable output voltage range. the switch is organized into nine 16:1 rbg multiplexers, with each being responsible for connecting an rgb input channel to its respective rgb output channel. decoding logic selects a single input (or none) in each multiplexer and connects it to its respective output. feedback around each multiplexer realizes a closed - loop differential - in , differential - out gain of +2. a second loop realizes a closed - loop common - mode - in gain of +1. each differential rgb input channel is buffered by a differential receiver, which is capable of accepting input cm voltages extending all the way to either supply rail. in addition to passing differential information, each receiver processes and routes input cm voltages. excess close d - loop receiver bandwidth reduces the receivers effect on the overall device bandwidth. the output stage is designed for f ast slew rate and settling time while driving a series - terminated cat5 cable. unlike competing multiplexer designs, the small signal bandwidth closely approaches the large signal bandwidth. the outputs of the ad8175 can be disabled to minimize on - chip power dissipation. when disabled, t here is a feedback network of approximately 2 .7 k between the differential outputs. this high impedance allows multiple ics to be bussed together without additional buffering. care must be taken to reduce output capacitance, which can result in overshoot and frequency - domain peaking. a series of internal amplifiers drive internal nodes such that wideband high impedance is presented at the disabled output, even while the output bus experiences fast signal swings. when the outputs are disabled and driven ext ernally, the voltage applied to them should not exceed the valid out put swing range for the ad8175 in order to keep these internal amplifiers in their linear range of operation. applying excessive differential voltages to the disabled outputs can cause dam age to the ad8175 and should be avoided (see the absolute maximum ratings section of this data sheet for guidelines). the connectivity of the ad8175 is controlled by a f lexible ttl - compatible logic interface. either parallel or serial loading into a first rank of latches preprograms each output. a global update signal moves the programming data into the second rank of latches, simultaneously updating all outputs. in ser ial mode, a serial - out pin allows devices to be daisy - chained together for a single - pin programming of multiple ics. a power - on reset pin is available to avoid bus conflicts by disabling all outputs. this power - on reset clears the second rank of latches, b ut does not clear the first rank of latches. a broadcast parallel programming feature is available in parallel mode to quickly clear the f irst rank . in serial mode, pre programming individual inputs is not possible and the entire shift register needs to be flushed. a global chip - select pin gates the input clock and the global update signal to the second rank of buffers. the ad8175 can operate on a single +5 v supply, powering both the signal path ( with the vpos/vneg supply pins) and the control logic interfa ce (with the vdd/dgnd supply pins). split supply operation is possible with 2.5 v supplies in order to easily interface to ground - referenced video signals. in this case, a flexible logic interface allows the control logic supplies (vdd/dgnd) to be run off +5 v/0 v to +3.3 v/0 v while the analog core remains on split supplies. additional flexibility in the analog output common - mode level (vocm_cmencoff) and output black level (vblk) facilitates operation with unequally split supplies. if +3 v/ ? 2 v supplies to +2 v/ ? 3 v supplies are desired, the output cm can still be set to 0 v for ground - referenced video signals. data sheet ad8175 rev. b | page 27 of 40 applications operating modes depending on the state of the cmenc logic input, the ad8175 can be set in either of two differential-in, differential-out operat- ing modes. an additional application is possible by tapping the outputs single-ended and making use of the decoded h and v outputs. middle-of-cat5-run application, cm encoding turned off in this application, the ad8175 is placed somewhere in the middle of a cat5 run. by tying cmenc low, the cm of each rgb differential pair is removed through the device (or turned off), while the overall cm at the output is defined by the reference value vocm_cmencoff. in this mode of operation, cm noise is removed, while the intended differential rgb signals are buffered and passed to the outputs. the ad8175 is placed in this operation mode when used in a sync-on color scheme. figure 46 shows the voltage levels and cm handling for a single input channel connected to a single output channel in a middle- of-cat5-run application with cm encoding turned off. cm r cm b diff. r diff. b input overall cm cm g diff. g cmenc ad8175 cm r cm b diff. r diff. b output overall cm cm g diff. g vocm_cmencoff 06478-019 figure 46. ad8175 in a middle-of-cat 5-run application, cm encoding off (note that in this application, the h and v outputs, though asserted, are not used) inputs vblk and vocm_cmencoff allow the user complete flexibility in defining the output cm level and the amount of overlap between the positive and negative phases, thus maximizing output head room usage. whenever vblk differs from vocm_cmencoff by more than approximately 100 mv, a differential voltage diff is added at the outputs according to the expression diff = vblk ? vocm_cmencoff. conversely, whenever the difference between vblk and vocm_cmencoff is less than approximately 100 mv, no differential voltage is added at the outputs. as a first example, refer to figure 47. the positive phase of a differential output is shown by the solid line, while the negative phase is shown by the dashed line. the input to the crosspoint is a positive differential pulse with a low level of 0 v and a high level of 0.7 v. the positive and negative outputs are shown with vocm_cmencoff and vblk both set to 0 v. (note that both pulses have been slightly shifted off the 0 v line for clarity.) 0.7v ?0.7v negative phase positive phase v blk = 0v v ocm_cmencoff = 0v 06478-020 figure 47. output for 0 v to 0.7 v input differential pulse, vblk = 0 v, vocm_cmencoff = 0 v as a second example, refer to figure 48. vcom_cmencoff is set to 0.35 v, while vblk is set to ?0.35 v. the input is still a differential pulse with a low level of 0 v and a high level of 0.7 v. note how the positive phase and the negative phase are now shifted with respect to each other by an amount equal to vblk C vocm_cmencoff or ?0.35 v ? 0.35 v = ?0.7 v. since the negative output phase spans the same voltage range as the positive output phase, the usable voltage range for single- ended applications is effectively doubled over the previous example. (note that the output pulses have been slightly shifted with respect to each other for clarity.) 0.7v negative phase positive phase v blk = ?0.35v v ocm_cmencoff = 0.35v 0v 06478-021 figure 48. output for 0 v to 0.7 v input differential pulse, vblk = ?0.35 v, vocm_cmencoff = 0.35 v middle-of-cat5-run application, cm encoding turned on in this application, the ad8175 is also placed somewhere in the middle of a cat5 run, although the common-mode handling is different. by tying cmenc high, the cm of each rgb input is passed through the part, while at the same time, the overall output cm is stripped and set equal to the voltage applied at the vocm_cmencon pin. the ad8175 is placed in this operation mode when used with a sync-on cm scheme. although asserted, the h and v outputs are not used in this application. figure 49 shows the voltage levels and cm handling for a single input channel connected to a single output channel in a middle-of- cat5-run application with cm encoding turned on. ad8175 data sheet rev. b | page 28 of 40 cm r cm b dif f . r dif f . b input overall cm cm g dif f . g cmenc ad8175 cm r cm b dif f . r dif f . b output overall cm cm g dif f . g vocm_cmencon 06478-022 figure 49 . ad8175 in middle - of - cat5 - r un application, cm encoding on (note that in this application, the h and v outputs, though asserted, are not used) in this operation mode , the difference diff = vblk ? vocm_cmencoff still adds an output differential voltage, as described in the previous section . end - of - cat5 - run, cm encoding turned off in this application, each ad8175 output is tapped single - ended at the positive phase and followed by a fast buf fer to drive a monitor at the end of a cat5 run (a suitable choic e is the ad8003 set up in a non inverting configuration with gain of +4). the h and v outputs can then be used to drive the monitors sync inputs directly. the relationship between the incomin g sync - on cm signaling and the h and v syncs is defined according to table 16. table 16 . h and v sync truth table (v pos /v neg = 2.5 v) cm r cm g cm b h v 0.5 0 0 low high 0 0.5 ?0.5 low low ?0.5 0.5 0 high low 0 ?0.5 0.5 high high the following two statements are equivalent to the truth table ( table 16) in producing h and v for all allowable cm inputs: 1. h sync is high when the cm of blue is larger than the cm of red . 2. v sync is high when the combined cm of red and blue is larger then the cm of green. programming the ad8175 has two options for changing the programming of the crosspoint matrix. in the first option, a serial word of 45 bits can be provided that updates the entire matrix each time. the second option allows for c hanging a single outputs programming via a parallel interface. the serial option requires fewer signals, but more time (clock cycles) for changing the programming; the parallel programming technique requires more signals, but allows for changing a single output at a time, therefore requiring fewer clock cycles. serial programming description the serial programming mode uses the device pins cs , clk , serin, update , and ser /par. the first step is to enable the clk on by pulling cs low. next, ser /par is pulled low to enable the serial programming mode. the parallel clock we should be held high during the entire serial programming operation. the update signal should be high during the time that data is shifted into the devices serial port. although the data still shifts in when update is low, the transparent, asynchronou s latches allow the shifting data to reach the matrix. this causes the matrix to try to update to every intermediate state as defined by the shifting data. the data at serin is clocked in at every falling edge of clk . a total of 45 bits m ust be shifted in to complete the programming. a total of five bits must be supplied for each of the nine rgb output channels an output enable bit (d4) and four bits (d3 to d0) , which determine the input channel. if d4 is low (output disabled), the four as sociated bits (d3 to d0) do not matter, because no input will be switched to that output. the most - significant - output - address data is shifted in first, with the enable bit (d4) shifted in first, followed by the input address (d3 to d0) entered sequentially with d3 first and d0 last. each remaining output is programmed sequentially, until the least - significant - output - address data is shifted in. at this point, update can be taken low, which causes the programming of the device according to t he data that was just shifted in. the update latches are asynchronous and when update is low, they are transparent. data sheet ad8175 rev. b | page 29 of 40 if more than one ad8175 device is to be serially programmed in a system, the serout signal from one dev ice can be connected to the serin of the next device to form a serial chain. all of the clk , update , and ser /par pins should be connected in parallel and operated as described above. the serial data is input to the serin pin of the first device of the chain, and it will ripple through to the last. therefore, the data for the last device in the chain should come at the beginning of the programming sequence. the length of the programming sequence is 45 bit s times the number of devices in the chain. cs gates the clk and update signals, so that when cs is held high , both clk and update are held in their inactive high state, while when cs is held low, both clk and update function normally. parallel programming description when using the parallel programming mode, it is not necessary to reprogram the en tire device when making changes to the matrix. in fact, parallel programming allows the modification of a single output or more at a time. since this takes only one we / update cycle, significant time savings can be reali zed by using parallel programming. one important consideration in using parallel programming is that the rst signal does not reset all registers in the ad8175. when taken low, the rst signal only sets each output to the disabled state. this is helpful during power - up to ensure that two parallel outputs are not active at the same time. after initial power - up, the internal registers in the device generally have random data, even though the rst signal has b een asserted. if parallel programming is used to program one output, then that output will be properly programmed, but the rest of the device will have a random program state depending on the internal register content at power - up. therefore, when using par allel programming, it is essential that all outputs be programmed to a desired state after power - up. this ensures that the programming matrix is always in a known state. from then on, parallel programming can be used to modify a single output or more at a time. in similar fashion, if update is taken low after initial power - up, the random power - up data in the shift register will be programmed into the matrix. therefore, in order to prevent the crosspoint from being programmed into an unknow n state, do not apply a logic level to update after power is initially applied. programming the full shift register once to a desired state, by either serial or parallel programming after initial power - up, eliminates the possibility of pr ogramming the matrix to an unknown state. the chip s elect ( cs ) feature is not applicable in parallel programming mode; in other words, it is possible to program the ad8175 in parallel mode when the part is deselected. refer to the logic diagram shown in figure 7 , which shows that the cs feature gates the serial clock and has no bearing on parallel mode programming. shared we lines should therefore not be used in parallel programming mode. to ch ange an outputs programming via parallel programming, ser /pa r , update , and clk should all be taken high . the parallel clock, we , should start in the high state. the 4 - bit address of t he output to be programmed should be put on a3 to a0. data b it d3 to d ata b it d0 should contain the information that identifies the input that gets programmed to the output that is addressed. data b it d4 determines the enabled state of the output. if d4 is low (output disabled), then the data on d3 to d0 does not matter. after the desired address and data signals have been established, they can be latched in to the shift register by a high - to - low transition of the we signal. t he matrix is n ot programmed , however, until the update signal is taken low. it is thus possible to latch in new data for several or all of the outputs first via successive negative transitions of we while update is held high, and then have all the new data take effect when update goes low. this is the technique that should be used when programming the device for the first time after power - up when using parallel programming. reset when powering u p the ad8175, it is usually desirable to have the outputs come up in the disabled state. the rst pin, when taken low, causes all outputs to be in the disabled state. however, the rst signal does not reset all registers i n the ad8175. this is important when operating in the parallel programming mode. r efer to the serial programming description section for information about programming internal registers after power - up. serial programming programs the entire matrix each time, so no special considerations apply. since the data in the shift register is random after power - up, it should not be used to program the matrix, or the matrix can e nter unknown states. to prevent this, do not apply a logic low signal to update initially after power - up. the shift register should first be loaded with the desired data, and only then can the update be taken low to prog ram the device. the rst pin has a 20 k pull - up resistor to vdd that can be used to create a simple power - up reset circuit. a capacitor from rst to ground holds rst low for some time while the rest of t he device stabilizes. the low condition causes all the outputs to be disabled. the capacitor then charges through the pull - up resistor to the high state, thus allowing full programming capability of the device. broadcast the ad8175 logic interface has a br oadcast mode, in which all first rank latches can be simultaneously parallel - programmed to the same data in one write - cycle. this is especially useful in clearing random first rank data after power - up. to access the broadcast mode, the part is parallel - pro grammed using the device pins we , a0 to a3, d0 to d4 and update . the only ad8175 data sheet rev. b | page 30 of 40 difference is that the ser /par pin is held low, as if serial programming were taking place. by holding clk hig h, no serial clocking will occur, and instead, the we can be used to clock all first rank latches in the chip at once. differential and s ingle - e nded o peration although the ad8175 has fully differential inputs and outputs, it can also be o pera ted in a single - ended fashion. single - ended and differential configurations are discussed below, along with implications on gain, impedances, and terminations. differential input each differential input to the ad8175 is applied to a differential receiver. these receivers allow the user to drive the inputs with an uncertain common - mode voltage, such as from a remote source over twisted pair. the receivers respond only to the differe nces in input voltages and restore an internal common - mode suitable for the internal signal path. noise or crosstalk, which affect each receivers inputs equally, are rejected by the input stage, as specified by its common - mode rejection ratio (cmrr). fur thermore, the overall common - mode voltage of all three differential pairs comprising an rgb channel is processed and rejected by a separate circuit block. for example, a static discharge or a resistive voltage drop in a middle - of - cat5 - run with sync - on cm s ignaling coupling into all three pairs in an rgb channel are rejected at the output of the ad8175, while the sync - on cm signals are allowed through the switch. the circuit configuration used by the differential input receivers is similar to that of several analog devices general - purpose differential amplifiers, such as the ad8131 . the topology is that of a voltage - feedback amplifier with internal gain resistors. the input differential impedance for each receiver is 5 k in parallel with 10 k or 3.33 k, as shown in figure 50. in+ in? r g r g r cm rcvr r f r f out? out+ to switch matrix 06478-023 figure 50 . input receiver equivalent circuit this impedance creates a small differential termination error if the user does not account for the 3.33 k parallel element. however, this error is less than 1% in most cases. additionally, the source impedance driving the ad8175 appears in parallel with t he internal gain - setting resistors, such that there may be a gain error for some values of source resistance. the ad8175 is adjusted such that its gain is correct when driven by a back - terminated cat5 cable (25 effective impedance to ground at each input pin, or 100 differential source impedance across pairs of input pins). if a different source impedance is presented , the differential gain of the ad8175 can be calculated as s dm r g + = k 5 . 2 k 525 . 2 where r s is the effective impedance to ground at each in put pin. when operating with a differential input, care must be taken to keep the common - mode, or average, of the input voltages within the linear operating range of the ad8175 receiver. for the ad8175 receiver, this common - mode range can extend rail - to - r ail, provided the differential signal swing is small enough to avoid forward biasing the esd diodes (it is safest to keep the common - mode plus differential signal excursions within the supply voltages of the part). the input voltage of the ad8175 is linear for 1 v of differential input voltage difference (this limitation is primarily due to ability of the output to swing close to the rails, since the differ - ential gain through the part is +2). beyond this level, the signal path will saturate and limit the signal swing. this is not a desired operation, as the supply current will increase and the signal path will be slow to recover from clipping. the absolute maximum allowed differential input signal is limited by long - term reliability of the input stage. the limits in the absolute maximum ratings section of the data sheet should be observed in order to avoid degrading device performance permanently. ac coupling of input s it is possible to ac - couple the inputs of the ad8175 receiver, so that bias current does not need to be supplied externally. a capacitor in series with the inputs to the ad8175 creates a high - pass filter with the input impedance of the device. this capac itor needs to be sized large enough so that the corner frequency includes all frequencies of interest. single - e nded input the ad8175 input receiver can be drive n single - endedly (unbalanced). single - ended inputs apply a component of common - mode signal to th e receiver inputs, which is then rejected by the receiver (see the specifications section for common - mode - to - differential - mode ratio of the part). the single - ended input resistance r in differs from the differential i nput impedance, and is equal to ) ( 2 1 f g f g in r r r r r + ? = w ith r g and r f as shown in figure 50. note that this value is smaller than the differential input resistance, but it is larger than r g . the difference is due to the component of common - mode level applied to the receiver by single - ended inputs. a second, smaller component of input resistance (r cm , also shown in figure 50) is present across the inputs in both single - ended and differential operation. in single - ended operation , an input is driven, while the undriven input is ofte n tied to midsupply or ground. since data sheet ad8175 rev. b | page 31 of 40 signal - frequency current flows at the undriven input, such input should be treated as a si gnal line in the board design. for example, in order to achieve best dynamic performance , the undriven input should be terminated with an impedance matching that seen by the part at the driven input. differential output benefits of differential operation the ad8175 has a fully - differential switch core with differential outputs. the two output voltages move in opposite directions, wi th a differential feedback loop maintaining a fixed output stage differential gain of +2. this differential output stage provides improved crosstalk cancellation due to parasitic coupling from one output to another being equal and out of phase. additionall y, if the output of the device is utilized in a differential design, then noise, crosstalk, and offset voltages generated on - chip that are coupled equally into both outputs are reduced by the common - mode rejection ratio of the next device in the signal cha in. by utilizing the ad8175 outputs in a differential application, the best possible noise and offset specifications can be realized. common - mode gain the common - mode, or average voltage of pairs of output signals, is set by the voltage on the vocm_cmencoff pin when common - mode encoding is off (cmenc is logic low), or by the voltage on the vocm_cmencon pin when common - mode encoding is on (cmenc is logic high). note that in the latter case, vcom_cmencon sets the overall common - mode of rgb triplets of differential outputs, while the individual common - mode of each rgb output is free to change. vcom_ cmencon and vcom_cmencoff are typically set to midsu pply (often ground), but can be moved approximately 0.5 v in order to accommodate cases where the desired output common - mode voltage may not be midsupply (as in the case of unequal split supplies). adjusting the output common - mode voltage beyond 0.5 v ca n limit differential swing internally below the specifications on the data sheet. the overall common - mode of the output voltages follow s the voltage applied to vocm_cmencon or vcom_cmencoff, implying a gain of +1. likewise, sync - on common - mode signaling is carried through the ad8175 (cmenc must be in its high state), implying a gain of +1 for this path as well. the common - mode reference pins are analog signal inputs, common to all output stages on the device. they require only small amounts of bias current, but noise appearing on these pins is buffered to all the output stages. as such, they should be connected to low noise, low impedance voltage references to avoid being sources of noise, offset, and crosstalk in the signal path. termination the ad8175 is designed to drive 100 terminated to ground on each output (or an effective 200 differential) while meeting data sheet specifications over the specified operating temperature range, if care is taken to observe the maximum power derating curves. te rm ina tion at the load end is recommended to shorten settling time and for best signal integrity. in differential signal paths, it is often desirable to series - terminate the outputs, with a resistor in series with each output. a side effect of termination is an attenuation of the output signal by a factor of two. in this case, gain is usually necessary somewhere else in the signal path to restore the signal level. whenever a differential output is used single - ended, it is desirable to terminate the used single - en ded output with a series resistor, as well as to place a resistor on the unused output to match the load seen by the used output. when disabled, the outputs float to midsupply. a small current is required to drive the outputs away from their midsupply sta te. this current is easily provided by an ad8175 output (in its enabled state) bussed together with the disabled output. exceeding the allowed output voltage range may saturate internal nodes in the disabled output, and consequently an increase in disabled output current may be observed. single - ended output usage the ad8175 output pairs can be used single - ended, taking only one output and not using the second. this is often desired to reduce the routing complexity in the design, or because a single - ended lo ad is being driven directly. this mode of operation produces good results, but has some shortcomings when compared to taking the output differentially. when observing the single - ended output, noise that is common to both outputs appears in the output signa l. when observing the output single - ended, the distribution of offset voltages will appear greater. in the differential case, the difference between the outputs when the difference between the inputs is zero is a small differential offset. this offset is created from mismatches in devices in the signal path. in the single - ended case, this differential offset is still observed, but an additional offset component is also relevant. this additional component is the common - mode offset, which is the difference b etween the average of the outputs and the output common - mode reference. this offset is created by mismatches that affect the signal path in a common - mode manner. a differential receiver rejects this common - mode offset voltage, but in the single - ended case, this offset is observed with respect to the signal ground. the single - ended output sums half the differential offset voltage and all of the common - mode offset voltage for a net increase in observed offset. single - ended gain the ad8175 operates as a closed - loop differential amplifier. the primary control loop forces the difference between the output terminals to be a ratio of the difference between the ad8175 data sheet rev. b | page 32 of 40 input terminals. one output increases in voltage, while the other decreases an equal amount to make the to tal output voltage difference correct. the average of these output voltages is forced to the voltage on the common - mode reference terminal (vocm_cmencoff or vocm_cmencon) by a second control loop. if only one output terminal is observed with respect to the common - mode reference terminal, only half of the difference voltage will be observed. this implies that when using only one output of the device, half of the differential gain is observed. an ad8175 taken with single - ended output appears to have a gain of +1. it is important to note that all considerations applying to the used output phase regarding output voltage headroom, apply unchanged to the complement output phase even if this is not actually used. termination when operating the ad8175 with a singl e - ended output, the preferred output termination scheme is to refer the load to the output common - mode. a series - termination can be used, at an additional cost of one half the signal gain. in single - ended output operation, the complementary phase of the o utput is not used, and may or may not be terminated locally. although the unused output can be floated to reduce power dissipation, there are several reasons for terminating the unused output with a load resistance matched to the load on the signal output. one component of crosstalk is magnetic coupling by mutual inductance between output package traces and bond wires that carry load current. in a differential design, there is coupling from one pair of outputs to other adjacent pairs of outputs. the differe ntial nature of the output signal simultaneously drives the coupling field in one direction for one phase of the output, and in an opposite direction for the other phase of the output. these magnetic fields do not couple equally into adjacent output pairs due to different proximities, but they do destructively cancel the crosstalk to some extent. if the load current in each output is equal, this cancellation will be greater and less adjacent crosstalk will be observed (regardless of whether the second outpu t is actually being used). a second benefit of balancing the output loads in a differential pair is to reduce fluctuations in current requirements from the power supply. in single - ended loads, the load currents alternate from the positive supply to the neg ative supply. this creates a parasitic signal voltage in the supply pins due to the finite resistance and inductance of the supplies. this supply fluctuation appears as crosstalk in all outputs, attenuated by the power supply rejection ratio (psrr) of the device. at low frequencies, this is a negligible component of crosstalk, but psrr falls off as frequency increases. with differential, balanced loads, as one output draws current from the positive supply, the other output draws current from the negative su pply. when the phase alternates, the first output draws current from the negative supply and the second from the positive supply. the effect is that a more constant current is drawn from each supply, such that the crosstalk - inducing supply fluctuation is m inimized. a third benefit of driving balanced loads can be seen if one considers that the output pulse response changes as load changes. the differential signal control loop in the ad8175 forces the difference of the outputs to be a fixed ratio to the diff erence of the inputs. if the two output responses are different due to loading, this creates a difference that the control loop sees as signal response error, and it will attempt to correct this error. this distorts the output signal from the ideal respons e compared to the case when the two outputs are balanced. decoupling the signal path of t he ad8175 is based on high open - loop gain amplifiers with negative feedback. dominant - pole compensation is used on - chip to stabilize these amplifiers over the range of expected applied swing and load conditions. to guarantee this designed stability, proper supply decoupling is necessary with respect to both the differential control loops and the common - mode control loops of the signal path. signal - generated currents mus t return to their sources through low impedance paths at all frequencies in which there is still loop gain (up to 700 mhz at a minimum). the signal path compensation capacitors in the ad8175 are connected to the vneg supply. at high frequencies, this limit s the power supply rejection ratio (psrr) from the vneg supply to a lower value than that from the vpos supply. if given a choice, an application board should be designed such that the vneg power is supplied from a low inductance plane, subject to a least amount of noise. vocm_cmencon and vocm_cmencoff are high speed common - mode control loops of all output drivers. in the single - ended output sense, there is no rejection from noise on these inputs to the outputs. for this reason, care must be taken to produc e low noise sources over the entire range of frequencies of interest. this is not only important to single - ended operation, but to differential operation, as there is a common - mode - to - differential gain conversion that becomes greater at higher frequencies. vocm_cmencon and vocm_cmencoff are internally buffered to prevent transient currents from flowing into or out of these inputs and becoming sources of crosstalk, by acting on their respective source impedances. data sheet ad8175 rev. b | page 33 of 40 power dissipation calculation of power dissipation 06478-036 ambient temperature (c) maximum power (w) 3 4 5 6 7 8 9 10 15 25 35 45 55 65 75 85 t j = 150c figure 51. maximum die power dissipation vs. ambient temperature the curve in figure 51 was calculated from ja ambient max junction maxd t t p ? ? ? , , (1) as an example, if the ad8175 is enclosed in an environment at 45 c (t a ), the total on-chip dissipation under all load and supply conditions must not be allowed to exceed 7.0 w. when calculating on-chip power dissipation, it is necessary to include the power dissipated in the output devices due to current flowing in the loads. for a sinusoidal output about ground and symmetrical split supplies, the on-chip power dissipation due the load can be approximated by ? ? rms output rms utput o pos outputd i vv p , , , ? ?? (2) for nonsinusoidal output, the power dissipation should be calculated by integrating the on-chip voltage drop across the output devices multiplied by the load current over one period. the user can subtract the quiescent current for the class ab output stage when calculating the loaded power dissipation. for each output stage driving a load, subtract a quiescent power, according to quiescent output neg pos output dq ivv p , , ) ( ??? (3) where i output, quiescent = 1.65 ma for each single-ended output pin for the ad8175. for each disabled rgb output channel, the quiescent power supply current in vpos and vneg drops by approximately 34 ma. q npn qpnp v neg v pos v output i output i o, quiescent i o, quiescent 06478-025 figure 52. simplified output stage example for the ad8175, with an ambient temperature of 85c, all nine rgb output channels driving 1 v rms into 100 loads, and power supplies at 2.5 v, follow these steps: 1. calculate power dissipation of ad8175 using data sheet quiescent currents. neglecting v dd current, as it is insignificant. ? ? ? ? vneg neg vpos pos quiescent d iviv p ? ?? ? , (4) ? ? ? ? w3ma600v5.2ma600v5.2 , ? ? ?? ? quiescent d p 2. calculate power dissipation from loads. for a differential output and ground-referenced load, the output power is symmetrical in each output phase. ? ? rms output rms output pos outputd i vv p , , , ? ? ? (5) ? ? ?? mw15100/v1v1v5.2 , ? ? ? ? outputd p there are 27 output pairs, or 54 output currents. w81.0mw1554 , ? ? ? outputd np 3. subtract quiescent output stage current for number of loads (54 in this example). the output stage is either standing or driving a load, but the current only needs to be counted once (valid for output voltages > 0.5 v). ? ? quiescent output neg pos output dq ivv p , , ? ? ? (6) ? ? mw25.8ma65.1v)5.2(v5.2 , ? ?? ? ? output dq p there are 27 output pairs, or 54 output currents. w45.0mw25.854 , ? ? ? output dq np 4. verify that the power dissipation does not exceed the maximum allowed value. output dq outputd quiescent d chipond np np p p , , , , ? ? ? ? (7) w36.3w45.0w81.0w3 , ? ? ? ? ? chipond p from figure 51 or equation 1, this power dissipation is below the maximum allowed dissipation for all ambient temperatures up to and including 85c. ad8175 data sheet rev. b | page 34 of 40 in a general cas e, the power delivered by the digital supply and dissipated into the digital output devices has to be taken into account following a similar derivation. however, since the loads driven by the h and v outputs is high and since the voltage at these outputs t ypically sits close to either rail, the correction to t he on - chip power estimate is small. furthermore, the h and v outputs are active only briefly during sync generation and returned to digital ground thereafter. short - circuit output conditions although t here is short - circuit current protection on the ad8175 outputs, the output current can reach values of 80 ma into a grounded output. any sustained operation with too many shorted outputs can exceed the maximum die temperature and can result in device fail ure (see the absolute maximum ratings section ). crosstalk many systems (such kvm switches) that handle numerous analog signal channels have strict requirements for keeping the various signals from influencing any of the other signals in the system. crosstalk is the term used to describe the coupling of the signals of other nearby channels to a given channel. when there are many signals i n close proximity in a system, as is undoubtedly the case in a system that uses the ad8175, the crosstalk issues can be quite complex. a good understanding of the nature of crosstalk and some definition of terms is required in order to specify a system tha t uses one or more crosspoint devices. types of crosstalk crosstalk can be propagated by means of any of three methods. these fall into the categories of electric field, magnetic field, and the sharing of common impedances. this section explain s these effe cts. every conductor can be both a radiator of electric fields and a receiver of electric fields. the electric field crosstalk mechanism occurs when the electric field created by the transmitter propagates across a stray capacitance ( for example , free space) and couples with the receiver and induces a voltage. this voltage is an unwanted crosstalk signal in any channel that receives it. currents flowing in conductors create magnetic fields that circulate around the currents. these magnetic fields then g enerate voltages in any other conductors whose paths they link. the undesired induced voltages in these other channels are crosstalk signals. the channels that crosstalk can be said to have a mutual inductance that couples signals from one channel to anoth er. the power supplies, grounds, and other signal return paths of a multi channel system are generally shared by the various channels. when a current from one channel flows in one of these paths, a voltage that is developed across the impedance becomes an i nput crosstalk signal for other channels that share the common impedance. all these sources of crosstalk are vector quantities, so the magnitudes cannot simply be added together to obtain the total crosstalk. in fact, there are conditions where driving add itional circuits in parallel in a given configuration can actually reduce the crosstalk. the fact that the ad8175 is a fully - differential design means that many sources of crosstalk either destructively cancel, or are common - mode to the signal and can be r ejected by a differential receiver. areas of crosstalk a practical ad8175 circuit must be mounted to an actual circuit board in order to connect it to power supplies and measurement equipment. great care has been taken to create an evaluation board (availa ble upon request) that adds minimum crosstalk to the intrinsic device. this, however, raises the issue that a systems crosstalk is a combi nation of the intrinsic crosstalk of the devices in addition to the circuit board to which they are mounted. it is im portant to try to separate these two areas when attempting to minimize the effect of crosstalk. in addition, crosstalk can occur am ong the inputs to a crosspoint and among the outputs. it can also occur from input to output. techniques are discussed in the following sections for diagnos - ing which part of a system is contributing to crosstalk. measuring crosstalk crosstalk is measured by applying a signal to one or more channels and measuring the relative strength of that signal on a desired selected channel . the measurement is usually expressed as db down from the magnitude of the test signal. the crosstalk is expressed by ? ? ? ? ? ? ? ? = ) ( ) ( log 20 10 s a s a xt test sel (8) where : s = j , the laplace transform variable a sel ( s ) is the amplitude of the crosstalk induced sign al in the selected channel . a test ( s ) is th e amplitude of the test signal. it can be seen that crosstalk is a f unction of frequency, but not a function of the magnitude of the test signal (to first order). in addition, the crosstalk signal has a phase relative to the test signal associated with it. a network analyzer is most commonly used to measure crosstalk over a frequency range of interest. it can provide both magnitude and phase information about the crosstalk signal. as a crosspoint system or device grows larger , the number of theoretical crosstalk combinations and permutations can become extremely large. for exampl e, in the case of the triple 16 9 matrix of the ad8175, we can look at the number of crosstalk terms that can be considered for a single channel, for data sheet ad8175 rev. b | page 35 of 40 example, input channel input0. input0 is programmed to connect to one of the ad8175 outputs where t he measurement can be made . first, the crosstalk terms associated with driving a test signal into each of the other 15 input channels can be measured one at a time, while applying no signal to input0. then, the crosstalk terms associated with driving a parallel test signal into all 15 other inputs can be measured two at a time in all possible combinations, then three at a time, and so on, until, finally, there is only one way to drive a test signal into all 15 other input channels in parallel. each of these cases is legitimately different from the others and might yield a unique value, depending on the resolution of the measurement system, but it is hardly prac tical to measure all these terms and then specify them. in addition, this describes the crosstalk matrix for just one input channel. a similar crosstalk matrix can be proposed for every other input. in addition, if the possible combinations and permutation s for connecting inputs to the other outputs (not used for measure - ment) are taken into consideration, the numbers rather quickly grow to astronomical proportions. if a larger crosspoint array of multiple ad8175s is constructed, the numbers grow larger sti ll. obviously, some subset of all these cases must be selected to be used as a guide for a practical measure of crosstalk. one common method is to measure all hostile crosstalk; this means that the crosstalk to the selected channel is measured while all ot her system channels are driven in parallel. in general, this yield s the worst crosstalk number, but this is not always the case, due to the vector nature of the crosstalk signal. other useful crosstalk measurements are those created by one nearest neighbor or by the two nearest neighbors on either side. these crosstalk measurements are generally higher than those of more distant channels, so they can serve as a worst - case measure for any other one - channel or two - channel crosstalk measurements. input and out put crosstalk capacitive coupling is voltage - driven (dv/dt), but is generally a constant ratio. capacitive crosstalk is proportional to input or output voltage, but this ratio is not reduced by simply reducing signal swings. attenuation factors must be cha nged by changing impedances (lowering mutual capacitance), or destructive canceling must be utilized by summing equal and ou t of phase components. for high input impedance devices such as the ad8175, capacitances generally dominate input - generated crosstal k. inductive coupling is proportional to current (di/dt), and often scale s as a constant ratio with signal voltage, but also show s a dependence on impedances (load current). inductive coupling can also be reduced by constructive canceling of equal and out of phase fie lds. in the case of driving low impedance video loads, output inductances contribute highly to output crosstalk. the flexible programming capability of the ad8175 can be used to diagnose whether crosstalk is occurring more on the input side or the output side. some examples are illustrative. a given input channel (input7 roughly in the middle for this example) can be programmed to drive output4 (exactly in the middle). the inputs to input7 are jus t terminated to ground (via 50 or 75 ) and no signal is applied. all the other inputs are driven in parallel with the same test signal (practically provided by a distribution amplifier), with all other outputs except output4 disabled. since grounded input7 is programmed to drive output4, no signal sh ould be present. any signal that is present can be attributed to the other 15 hostile input signals, because no other outputs are driven (they are all disabled). thus, this method measures the all - hostile input contribution to crosstalk into input7. of cou rse, the method can be used for other input channels and combinations of hostile inputs. for output crosstalk measurement, a single input channel is driven (input0, for example) and all outputs other than a given output (output4 in the middle) are programm ed to connect to input0. output4 is programmed to connect to input15 (far away from input0), which is terminated to ground. thus , output4 should not have a signal present since it is listening to a quiet input. any signal measured at the output4 can be at tributed to the output crosstalk of the other eight hostile outputs. again, this method can be modified to measure other channels and other crosspoint matrix combinations . effect of impedances on crosstalk the input side crosstalk can be influenced by the output impedance of the sources that drive the inputs. the lower the impedance of the drive source, the lower the magnitude of the crosstalk. the dominant crosstalk mechanism on the input side is capacitive coupling. the high impedance inputs do not have s ignificant current flow to create magnetically induced crosstalk. however, significant current can flow through the input termination resistors and the loops that drive them. thus, the pc board on the input side can contribute to magnetically coupled cross talk. from a circuit standpoint, the input crosstalk mechanism looks like a capacitor coupling to a resistive load. for low frequencies , the magnitude of the crosstalk is given by [ ] s c r xt m s = ) ( log 20 10 (9) where : r s is the source resistance . c m is the mutual capacitance between the test signal circuit and the selec ted circuit. s is the laplace transform variable. from equation 9, it can be observed that this crosstalk mechanism has a high - pass nature; it can also be minimized by reducing the cou pling capacitance of the input circuits and lowering the output impedance of the drivers. if the input is ad8175 data sheet rev. b | page 36 of 40 driven from a 75 terminated cable, the input crosstalk can be reduced by buffering this signal with a low output imped - ance buffer. on the output s ide, the crosstalk can be reduced by driving a lighter load. although the ad8175 is specified with excellent settling time when driving a properly terminated cat5, the crosstalk is higher than the minimum obtainable due to the high output currents. these c urrents induce crosstalk via the mutual inductance of the output pins and bond wires of the ad8175. from a circuit standpoint, this output crosstalk mechanism looks like a transformer with a mutual inductance between the windings that drives a load resisto r. for low frequencies, the magnitude of the crosstalk is given by ? ? ? ? ? ? ? ? = l xy r s m xt 10 log 20 (10) where : m xy is the mutual inductance of o utput x to o utput y . r l is the load res istance on the measured output. this crosstalk mechanism can be minimized by keeping the mutual inductance low and increasing r l . the mutual inductance can be kept low by increasing the spacing of the conductors and m inimizing their parallel length. pcb layout extreme care must be exercised to minimize additional crosstalk generate d by the system circuit board(s). the areas that must be carefully detailed are grounding, shielding, signal routing, and supply bypassing. the packaging of the ad8175 is designed to help keep the crosstalk to a minimum. on the bga substrate, each pair is carefully routed to predominately couple to each other, with shielding traces separating adjacent signal pairs. the ball grid array is arranged such that simil ar board routing can be achieved . input and output differential pairs are grouped by channel rath er than by color to allow for easy, convenient board routing. the input and output signals have minimum crosstalk if they are located between ground planes on layers above and below, and separated by ground in between. vias should be located as close to th e ic as possible to carry the inputs and outputs to the inner layer. the input and output signals surface at the input termination resistors and the output series back - termination resistors. to the extent possible, these signals should also be separated as soon as they emerge from the ic package. pcb termination layout as frequencies of operation increase, the importance of proper transmission line signal routing becomes more important. the bandwidth of the ad8175 is large enough that using high impedance routing does not provide a flat in - band frequency response for practical signal trace lengths. it is necessary for the user to choose a characteristic im pedance suitable for the applica - tion and properly terminate the input and output signals of the ad8175 . traditionally, video applications have used 75 single - ended environments. rf applications are generally 50 single - ended (and board manufactur ers have the most experience with this application). cat - 5 cabling is usually driven as differential pairs of 100 differential impedance. for flexibility, the ad8175 does not contain on - chip termina - tion resistors. this flexibility in application comes with some board layout challenges. the distance between the termination of the input transmission line and the ad8175 die is a high impedance stub, and causes reflections of the input signal. with some simplification, it can be shown that these reflections cause peaking of the input at regular intervals in frequency, dependent on the propagation speed (v p ) of the signal in the chosen board material and the distance (d) between the termination resistor and the ad8175. if the distance is great enough, these peaks can occur in - band. in fact, practical experience shows that these peaks are not high - q, and should be pus hed out to three or four times the desired bandwidth in order to not have an effect on the signal. for a board designer using fr4 (v p = 144 10 6 m/s), this means the ad8175 should be no more than 1.5 cm after the termination resistors, and preferably shou ld be placed even closer. the bga substrate routing inside the ad8175 is approxi - mately 1 cm in length and adds to the stub length, so 1.5 cm pcb routing equates to d = 2.5 10 C 2 m in the calculations. ( ) d v n f p peak 4 1 2 + = (11) where n = {0, 1, 2, 3, ...}. in some cases, it is difficult to place the termination close to the ad8175 due to space constraints, differential routing, and large resistor footprints. a preferable solution in this case is to main - tain a controlled transmission line past the ad8175 inputs and terminate the end of the li ne. this is known as fly - by termination . the input impedance of the ad8175 is large enough and stub length inside the package is small enough that this works well in practic e. implementation of fly - by input termination often includes bringing the signal in on one routing layer , then passing through a filled via under the ad8175 input ball, then back out to termination on another signal layer. in this case, care must be taken to tie the reference ground planes together near the signal via if the signal layers are referenced to different ground planes. data sheet ad8175 rev. b | page 37 of 40 ad8175 opn onn ipn inn 50? 06478-026 figure 53 . fly - by input termination (grounds for the two transmission lines shown must be ti ed toge ther close to the inn pin ) if multiple ad8175s are to be driven in parallel, a fly - by input termination scheme is very useful, but the distance from each ad8175 input to the driven input transmission line is a stub that should be minimized in length and pa rasitics using the discussed guidelines. when driving the ad8175 single - endedly, the undriven input is often terminated with a resistance in order to balance the input stage. it can be seen that by terminating the undriven input with a resistor of one - half the characteristic impedance, the input stage will be perfectly balanced (25 , for example, to balance the two parallel 50 terminations on the driven input). however, due to the feedback in the input receiver, there is high speed signal current leaving the undriven input. in order to terminate this high speed signal, proper transmission line techniques should be used. one solution is to adjust the trace width to create a transmission line of half the characteristic impedance and terminate the far end wi th this resistance (25 in a 50 system). this is not often practical as trace widths become large. in most cases, the best practical solution is to place the half - characteristic impedance resistor as close as possible (preferably less than 1.5 cm away) and to reduce the parasitics of the stub (by removing the ground plane under the stub, for example). in either case, the designer must decide if the layout complexity created by a balanced, terminated solution is preferable to simply grounding the undriven input at the ball with no trace. while the examples discussed so far are for input termination, the theory is similar for output back - termination. taking the ad8175 as an ideal voltage source, any distance of routing between the ad8175 and a back - termination resistor will be a n impedance mismatch that potentially creates reflections. for this reason, back - termination resistors should also be placed close to the ad8175. in practice, because back - termination resistors are series elements, they c an be place d close to the ad8175 outputs. finally, the ad817 5 pin out allows the user to bring the outputs out as surface traces to t he back - termination resistors. the designer can avoid creating stubs and reflections b y keeping the ad8175 output signal pat h on the surface of the board . a stub is created when a top - to - bottom via connection is made on the output signal path that is perpendicular to the signal flow. ad8175 data sheet rev. b | page 38 of 40 06478-053 pc 15-pin hd connector 15-pin hd connector four rgb, hv channels four rgb, hv channels in0 to in3 in4 to in7 four 15-pin hd connectors four 15-pin hd connectors three 15-pin hd connectors pc eight sma connectors twelve sma connectors four rj-45 connectors rj-45 connector rj-45 connector in8 to in11 cat5 pc 15-pin hd connectors four differential rgb with sync-on cm channels ribbon cable in14 to in15 signal generator/ network analyzer in12 to in13 high speed scope/ network analyzer differential rgb, hv differential rgb, hv channel two differential rgb channels rgb monitor rgb monitor differential rgb with sync-on cm out3 to out5 differential offset three rgb channels rgb, hv channel rgb, hv channel out6 out7 cat-5 vpos vdd gnd vneg to controller pc usb four ad8147 (g = +2) four ad8147 (g = +2) ad8003 (g = +4) ad8175 customer evaluation board three rgb, hv channels out8 usb national instruments controller board ad8175 dut in0 to in3 out3 to out5 out0 to out2 in4 to in7 out6 in8 to in11 out7 in12 to in13 out8 in14 to in15 three 15-pin hd connectors rgb monitor three rgb, hv channels three rgb, hv channels out0 to out2 ad8145 (g = +2) two gore headers gore header ad8147 (g = +2) evaluation board three hv pairs figure 54. evaluation board block diagram data sheet ad8175 rev. b | page 39 of 40 outline dimensions compliant t o jedec s t andards ms-034-aal-1 de t ai l a 0.70 0.60 0.50 bal l diameter t op view 1.00 bsc 1.00 ref 25.00 bsc sq coplanarity 0.20 max a b c d e f g h j k l m n p r t u v w y aa ab ac ad ae af detail a 1 2 3 4 5 6 7 8 9 10 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 11 seating plane a1 ball pad corner 27.20 27.00 sq 26.80 24.20 24.00 sq 23.80 051208-c a1 corner index area 2.45 2.28 2.08 0.50 nom 0.40 min 0.66 0.61 0.56 1.22 1.17 1.12 figure 55 . 676 - ball plastic ball grid array [p bga] (b - 676) dimensions shown in millimeters ordering guide model 1 temperature range package description package option ad8175abpz ? 40c to +85c 676- ball plastic ball grid array [pbga] b -676 ad8175 - eval z evaluation board 1 z = rohs compliant part. ad8175 data sheet rev. b | page 40 of 40 notes ? 2007 C 2011 analog devices, inc. all rights reserved. trademarks and registered trademarks are the property of their respective owners. d06478 - 0- 10/11(b) |
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